summaryrefslogtreecommitdiffstats
path: root/llvm/lib
Commit message (Collapse)AuthorAgeFilesLines
* [libFuzzer] simplify TracePC::HandleTrace even further. Also, when dealing ↵Kostya Serebryany2016-10-263-29/+5
| | | | | | with -exit_on_src_pos, symbolize every PC only once llvm-svn: 285223
* [AArch64] Avoid materializing constant 1 when generating cneg instructions.Chad Rosier2016-10-261-2/+13
| | | | | | | | | | | | | | | | | Instead of cmp w0, #1 orr w8, wzr, #0x1 cneg w0, w8, ne we now generate cmp w0, #1 csinv w0, w0, wzr, eq PR28965 llvm-svn: 285217
* [WebAssembly] Update the README.txt.Dan Gohman2016-10-261-9/+17
| | | | | | | | Update the README.txt with newer information, add a link to the Emscripten page explaining the current easiest way to use the LLVM wasm backend, and mention that other ways of using the LLVM wasm backend are in development. llvm-svn: 285215
* [MC] Fix comma typo in .loc parsingNirav Dave2016-10-261-1/+1
| | | | llvm-svn: 285214
* Reapply: "Remove debug location from common tail when tail-merging"Robert Lougher2016-10-261-2/+5
| | | | | | | | | | | | | | | | This reapplies revision 285093. Original commit message: The branch folding pass tail merges blocks into a common-tail. However, the tail retains the debug information from one of the original inputs to the merge (chosen randomly). This is a problem for sampled-based PGO, as hits on the common-tail will be attributed to whichever block was chosen, irrespective of which path was actually taken to the common-tail. This patch fixes the issue by nulling the debug location for the common-tail. Differential Revision: https://reviews.llvm.org/D25742 llvm-svn: 285212
* AMDGPU: Refactor processor definition to use ISA version featuresYaxun Liu2016-10-264-34/+118
| | | | | | | | | | | | | | Add missing ISA versions 7.0.2/8.0.4/8.1.0. to backend. Refactor processor definition to use ISA version features. Fixed ISA version for stoney. Based on Laurent Morichetti's patch. Differential Revision: https://reviews.llvm.org/D25919 llvm-svn: 285210
* Introduce updateDiscriminator interface to DILocation to make it cleaner ↵Dehao Chen2016-10-261-30/+7
| | | | | | | | | | | | | | assigning discriminators. Summary: This patch introduces updateDiscriminator to DILocation so that it can be directly called by AddDiscriminator. It also makes it easier to update the discriminator later. Reviewers: dnovillo, dblaikie, aprantl, echristo Subscribers: mehdi_amini, llvm-commits Differential Revision: https://reviews.llvm.org/D25959 llvm-svn: 285207
* Reapply "AMDGPU: Don't use offen if it is 0"Matt Arsenault2016-10-262-14/+100
| | | | | | This reverts r283003 llvm-svn: 285203
* AMDGPU: Fix counting si_mask_branch as 4 bytesMatt Arsenault2016-10-262-1/+1
| | | | llvm-svn: 285202
* Fix nondeterministic output in local stack slot alloc passMatt Arsenault2016-10-261-6/+16
| | | | | | | | | | This finds all of the references to a frame index in a function, and sorts by the offset. If multiple instructions use the same offset, nothing was breaking the tie for sorting. This avoids the test failures the reverted r282999 introduced. llvm-svn: 285201
* [InstCombine] clean up commonCastTransforms; NFCSanjay Patel2016-10-261-11/+9
| | | | | | | | 1. Use 'auto' with dyn_cast. 2. Variables start with a capital letter. 3. Use proper punctuation in comments. llvm-svn: 285200
* LegalizeDAG: Support promoting [US]DIV and [US]REM operationsTom Stellard2016-10-261-1/+18
| | | | | | | | | | | | | | | | | | Summary: AMDGPU will need this one i16 is added as a legal type. This is tested by: test/CodeGen/AMDGPU/sdiv.ll test/CodeGen/AMDGPU/sdivrem24.ll test/CodeGen/AMDGPU/udiv.ll test/CodeGen/AMDGPU/udivrem24.ll Reviewers: bogner, efriedma Subscribers: efriedma, wdng, llvm-commits Differential Revision: https://reviews.llvm.org/D25699 llvm-svn: 285199
* AMDGPU/SI: Don't emit multi-dword flat memory ops when they might access scratchTom Stellard2016-10-261-0/+16
| | | | | | | | | | | | | | Summary: A single flat memory operations that might access the scratch buffer can only access MaxPrivateElementSize bytes. Reviewers: arsenm Subscribers: kzhuravl, wdng, nhaehnle, yaxunl, tony-tye, llvm-commits Differential Revision: https://reviews.llvm.org/D25788 llvm-svn: 285198
* [X86] AVX512 fallback for floating-point scalar selectsZvi Rackover2016-10-261-0/+5
| | | | | | | | | | | | | Summary: In the case where of 'select i1 , f32, f32' or select i1, f64, f64 prefer lowering to masked-moves over branches. Fixes pr30561 Reviewers: igorb, aymanmus, delena Differential Revision: https://reviews.llvm.org/D25310 llvm-svn: 285196
* [AliasSetTracker] Make AST smarter about intrinsics that don't actually ↵Chad Rosier2016-10-261-0/+15
| | | | | | | | affect memory. Differential Revision: https://reviews.llvm.org/D25969 llvm-svn: 285191
* DebugInfo: support for DWARFv5 DW_AT_alignment attributeVictor Leschuk2016-10-263-1/+26
| | | | | | | | | | | | * Assume that clang passes non-zero alignment value to DIBuilder only in case when it was forced by C++11 'alignas', C11 '_Alignas' or compiler attribute '__attribute__((aligned (N)))'. * Emit DW_AT_alignment if alignment is specified for type/object. Differential Revision: https://reviews.llvm.org/D24425 llvm-svn: 285189
* [IndVarSimplify][DebugLoc] When widening the exit loop condition, correctly ↵Andrea Di Biagio2016-10-261-0/+5
| | | | | | | | | | | | | | | reuse the debug location of the original comparison. When the loop exit condition is canonicalized as a != compaison, reuse the debug location of the original (non canonical) comparison. Before this patch, the debug location of the new icmp was obtained from the loop latch terminator. This patch fixes the issue by correctly setting the IRBuilder's "current debug location" to the location of the original compare. Differential Revision: https://reviews.llvm.org/D25953 llvm-svn: 285185
* Revert r285181 "DebugInfo: support for DWARFv5 DW_AT_alignment attribute".Vassil Vassilev2016-10-263-26/+1
| | | | | | The commit broke the builds. llvm-svn: 285183
* DebugInfo: support for DWARFv5 DW_AT_alignment attributeVictor Leschuk2016-10-263-1/+26
| | | | | | | | | | | | * Assume that clang passes non-zero alignment value to DIBuilder only in case when it was forced by C++11 'alignas', C11 '_Alignas' or compiler attribute '__attribute__((aligned (N)))'. * Emit DW_AT_alignment if alignment is specified for type/object. Differential Revision: https://reviews.llvm.org/D24425 llvm-svn: 285181
* [AVX-512] Add scalar vfmsub/vfnmsub mask3 intrinsicsCraig Topper2016-10-261-0/+4
| | | | | | | | | | | | Summary: Clang's intrinsic header currently tries to negate the third operand of a vfmadd mask3 in order to create vfmsub, but this fails isel. This patch adds scalar vfmsub and vfnmsub mask3 that we can use instead to avoid the negate. This is consistent with the packed instructions. Reviewers: igorb, delena Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D25933 llvm-svn: 285173
* Cloning: Also clone global variable attached metadata.Peter Collingbourne2016-10-261-0/+5
| | | | llvm-svn: 285161
* [libFuzzer] simplify the code in TracePC::HandleTrace a bit moreKostya Serebryany2016-10-263-33/+18
| | | | llvm-svn: 285147
* [libFuzzer] simplify the code to print new PCsKostya Serebryany2016-10-264-16/+20
| | | | llvm-svn: 285145
* Utility functions for appending to llvm.used/llvm.compiler.used.Evgeniy Stepanov2016-10-255-99/+69
| | | | llvm-svn: 285143
* [libFuzzer] simplify the code in TracePC::HandleTraceKostya Serebryany2016-10-253-5/+9
| | | | llvm-svn: 285142
* [libFuzzer] add StandaloneFuzzTargetMain.c and a test for itKostya Serebryany2016-10-255-3/+62
| | | | llvm-svn: 285135
* [Sparc] Don't overlap variable-sized allocas with other stack variables.James Y Knight2016-10-251-3/+43
| | | | | | | | | | | | | | | | | | | | On SparcV8, it was previously the case that a variable-sized alloca might overlap by 4-bytes the last fixed stack variable, effectively because 92 (the number of bytes reserved for the register spill area) != 96 (the offset added to SP for where to start a DYNAMIC_STACKALLOC). It's not as simple as changing 96 to 92, because variables that should be 8-byte aligned would then be misaligned. For now, simply increase the allocation size by 8 bytes for each dynamic allocation -- wastes space, but at least doesn't overlap. As the large comment says, doing this more efficiently will require larger changes in llvm. Also adds some test cases showing that we continue to not support dynamic stack allocation and over-alignment in the same function. llvm-svn: 285131
* [codeview] support emitting indirect virtual base class informationBob Haarman2016-10-253-5/+13
| | | | | | | | | | | | | | | | Summary: Fixes PR28281. MSVC lists indirect virtual base classes in the field list of a class, using LF_IVBCLASS records. This change makes LLVM emit such records when processing DW_TAG_inheritance tags with the DIFlagVirtual and (newly introduced) DIFlagIndirect tags. Reviewers: rnk, ruiu, zturner Differential Revision: https://reviews.llvm.org/D25578 llvm-svn: 285130
* [DAGCombiner] Enable (urem x, (shl pow2, y)) -> (and x, (add (shl pow2, y), ↵Simon Pilgrim2016-10-251-3/+3
| | | | | | -1)) combine for splatted vectors llvm-svn: 285129
* [PGO] Fix select instruction annotationRong Xu2016-10-251-4/+13
| | | | | | | | | | | | | | | | Summary: Select instruction annotation in IR PGO uses the edge count to infer the branch count. It's currently placed in setInstrumentedCounts() where no all the BB counts have been computed. This leads to wrong branch weights. Move the annotation after all BB counts are populated. Reviewers: davidxl Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D25961 llvm-svn: 285128
* [DAGCombiner] Enable srem(x.y) -> urem(x,y) combine for vectorsSimon Pilgrim2016-10-251-4/+2
| | | | | | SelectionDAG::SignBitIsZero (via SelectionDAG::computeKnownBits) has supported vectors since rL280927 llvm-svn: 285123
* [DAGCombiner] Enable sdiv(x.y) -> udiv(x,y) combine for vectorsSimon Pilgrim2016-10-251-4/+2
| | | | | | SelectionDAG::SignBitIsZero (via SelectionDAG::computeKnownBits) has supported vectors since rL280927 llvm-svn: 285118
* [InstCombine] Resubmit the combine of A->B->A BitCast and fix for pr27996Guozhi Wei2016-10-252-0/+128
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The original patch of the A->B->A BitCast optimization was reverted by r274094 because it may cause infinite loop inside compiler https://llvm.org/bugs/show_bug.cgi?id=27996. The problem is with following code xB = load (type B); xA = load (type A); +yA = (A)xB; B -> A +zAn = PHI[yA, xA]; PHI +zBn = (B)zAn; // A -> B store zAn; store zBn; optimizeBitCastFromPhi generates +zBn = (B)zAn; // A -> B and expects it will be combined with the following store instruction to another store zAn Unfortunately before combineStoreToValueType is called on the store instruction, optimizeBitCastFromPhi is called on the new BitCast again, and this pattern repeats indefinitely. optimizeBitCastFromPhi only generates BitCast for load/store instructions, only the BitCast before store can cause the reexecution of optimizeBitCastFromPhi, and BitCast before store can easily be handled by InstCombineLoadStoreAlloca.cpp. So the solution to the problem is if all users of a CI are store instructions, we should not do optimizeBitCastFromPhi on it. Then optimizeBitCastFromPhi will not be called on the new BitCast instructions. Differential Revision: https://reviews.llvm.org/D23896 llvm-svn: 285116
* revert: "Remove debug location from common tail when tail-merging"Robert Lougher2016-10-251-5/+2
| | | | | | | | This reverts r285093, as it caused unexpected buildbot failures on clang-ppc64le-linux, clang-ppc64be-linux, clang-ppc64be-linux-multistage and clang-ppc64be-linux-lnt. Failing test ubsan/TestCases/TypeCheck/vptr.cpp. llvm-svn: 285110
* [libFuzzer] when mutating based on CMP traces also try adding +/- 1 to the ↵Kostya Serebryany2016-10-253-11/+10
| | | | | | desired bytes. Add another test for use_cmp llvm-svn: 285109
* [InstCombine] Ensure that truncated int types are legal.Sanjay Patel2016-10-251-4/+2
| | | | | | | | | | Fixes the FIXMEs in D25952 and rL285075. Patch by bryant! Differential Revision: https://reviews.llvm.org/D25955 llvm-svn: 285108
* [AArch64] Adjust the cost model for Exynos M1.Evandro Menezes2016-10-251-1/+1
| | | | | | Modify the maximum jump table size. llvm-svn: 285106
* [APFloat] Make APFloat an interface class to the internal IEEEFloat. NFC.Tim Shen2016-10-251-372/+244
| | | | | | | | | | | | | | | | | | | | | Summary: The intention is to make APFloat an interface class, so that later I can add a second implementation class DoubleAPFloat to correctly implement PPCDoubleDouble semantic. The interface of IEEEFloat is not public, and can be simplified (currently it's exactly the same as the old APFloat), but that belongs to a separate patch. DoubleAPFloat should look like: class DoubleAPFloat { const fltSemantics *Semantics; std::unique_ptr<APFloat> APFloats; // Two heap-allocated APFloats. }; There is no functional change, nor public interface change. Reviewers: hfinkel, chandlerc, iteratee, echristo, kbarton Subscribers: llvm-commits, mehdi_amini Differential Revision: https://reviews.llvm.org/D25536 llvm-svn: 285105
* Add option to specify minimum number of entries for jump tablesEvandro Menezes2016-10-251-3/+14
| | | | | | | | | | Add an option to allow easier experimentation by target maintainers with the minimum number of entries to create jump tables. Also clarify the name of the other existing option governing the creation of jump tables. Differential revision: https://reviews.llvm.org/D25883 llvm-svn: 285104
* Switch lowering: improve partitioning of jump tablesEvandro Menezes2016-10-251-14/+31
| | | | | | | | | | | When there's a tie between partitionings of jump tables, consider also cases that result in no jump tables, but in one or a few cases. The motivation is that many contemporary processors typically perform case switches fairly quickly. Differential revision: https://reviews.llvm.org/D25212 llvm-svn: 285099
* [LV] Sink scalar operands of predicated instructionsMatthew Simpson2016-10-251-13/+78
| | | | | | | | | | | | | When we predicate an instruction (div, rem, store) we place the instruction in its own basic block within the vectorized loop. If a predicated instruction has scalar operands, it's possible to recursively sink these scalar expressions into the predicated block so that they might avoid execution. This patch sinks as much scalar computation as possible into predicated blocks. We previously were able to sink such operands only if they were extractelement instructions. Differential Revision: https://reviews.llvm.org/D25632 llvm-svn: 285097
* Add -strip-nonlinetable-debuginfo capabilityMichael Ilseman2016-10-255-1/+338
| | | | | | | | | | | | | | | | | | | | | | | | This adds a new function to DebugInfo.cpp that takes an llvm::Module as input and removes all debug info metadata that is not directly needed for line tables, thus effectively stripping all type and variable information from the module. The primary motivation for this feature was the bitcode work flow (cf. http://lists.llvm.org/pipermail/llvm-dev/2016-June/100643.html for more background). This is not wired up yet, but will be in subsequent patches. For testing, the new functionality is exposed to opt with a -strip-nonlinetable-debuginfo option. The secondary use-case (and one that works right now!) is as a reduction pass in bugpoint. I added two new bugpoint options (-disable-strip-debuginfo and -disable-strip-debug-types) to control the new features. By default it will first attempt to remove all debug information, then only the type info, and then proceed to hack at any remaining MDNodes. Thanks to Adrian Prantl for stewarding this patch! llvm-svn: 285094
* Remove debug location from common tail when tail-mergingRobert Lougher2016-10-251-2/+5
| | | | | | | | | | | | | | The branch folding pass tail merges blocks into a common-tail. However, the tail retains the debug information from one of the original inputs to the merge (chosen randomly). This is a problem for sampled-based PGO, as hits on the common-tail will be attributed to whichever block was chosen, irrespective of which path was actually taken to the common-tail. This patch fixes the issue by nulling the debug location for the common-tail. Differential Revision: https://reviews.llvm.org/D25742 llvm-svn: 285093
* Fix 80-char violations. NFC.Michael Kuperstein2016-10-251-5/+10
| | | | llvm-svn: 285092
* [WebAssembly] Add immediate fields to call_indirect and memory operators.Dan Gohman2016-10-254-18/+26
| | | | | | | call_indirect, grow_memory, and current_memory now have immediate operands in the 0xd binary encoding. llvm-svn: 285085
* Move discriminator assignment to where it is used. (NFC)Dehao Chen2016-10-251-1/+1
| | | | llvm-svn: 285084
* [IndVarSimplify][Dwarf] When widening the IV increment, correctly set the ↵Andrea Di Biagio2016-10-251-0/+5
| | | | | | | | | | | | | | | debug loc. When indvars widened an induction variable, the debug location for the loop increment computation was incorrectly set equal to the debug loc of the loop latch terminator. This patch fixes the issue by propagating the correct location from the original loop increment instruction to the new widened increment. Differential Revision: https://reviews.llvm.org/D25872 llvm-svn: 285083
* Replace TimeValue by TimePoint in LegacyPassManager. NFC.Pavel Labath2016-10-251-5/+4
| | | | llvm-svn: 285081
* [EarlyCSE] Make MemorySSA memory dependency check more aggressive.Geoff Berry2016-10-251-16/+6
| | | | | | | | | | Now that MemorySSA keeps track of whether MemoryUses are optimized, use getClobberingMemoryAccess() to check MemoryUse memory dependencies since it should no longer be so expensive. This is a follow-up change to https://reviews.llvm.org/D25881 llvm-svn: 285080
* fix formatting; NFCSanjay Patel2016-10-251-13/+13
| | | | llvm-svn: 285078
OpenPOWER on IntegriCloud