summaryrefslogtreecommitdiffstats
path: root/llvm/lib
Commit message (Collapse)AuthorAgeFilesLines
* Relax dwarf line fragments. This fixes a crash in the included testcase.Rafael Espindola2010-11-071-13/+18
| | | | llvm-svn: 118365
* implement aliases for div/idiv that have an explicit A register operand,Chris Lattner2010-11-061-0/+20
| | | | | | implementing rdar://8431864 llvm-svn: 118364
* Add support for parsing register lists. We can't use a bitfield to keep track ofBill Wendling2010-11-061-22/+64
| | | | | | | | | | | the registers, because the register numbers may be much greater than the number of bits available in the machine's register. I extracted the register list verification code out of the actual parsing of the registers. This made checking for errors much easier. It also limits the number of warnings that would be emitted for cascading infractions. llvm-svn: 118363
* add aliases for movs between seg registers and mem. There are multipleChris Lattner2010-11-061-0/+5
| | | | | | | | | | different forms of this instruction (movw/movl/movq) which we reported as being ambiguous. Since they all do the same thing, gas just picks the one with the shortest encoding. Follow its lead here. This implements rdar://8208615 llvm-svn: 118362
* move the "sh[lr]d op,op" -> "shld $1, op,op" aliases to the .td file.Chris Lattner2010-11-062-10/+18
| | | | llvm-svn: 118361
* Return the base register of a register list for the "getReg()" method. This isBill Wendling2010-11-061-3/+8
| | | | | | | to satisfy the ClassifyOperand method of the Asm matcher without having to add a RegList type to every back-end. llvm-svn: 118360
* work-in-progressChris Lattner2010-11-061-7/+6
| | | | llvm-svn: 118358
* General cleanup:Bill Wendling2010-11-061-36/+21
| | | | | | | - Make ARMOperand a class so that some things are internal to the class. - Reformatting. llvm-svn: 118357
* go to great lengths to work around a GAS bug my previous patchChris Lattner2010-11-062-8/+8
| | | | | | | | | | | | | | | | exposed: GAS doesn't accept "fcomip %st(1)", it requires "fcomip %st(1), %st(0)" even though st(0) is implicit in all other fp stack instructions. Fortunately, there is an alias for fcomip named "fcompi" and gas does accept the default argument for the alias (boggle!). As such, switch the canonical form of this instruction to "pi" instead of "ip". This makes the code generator and disassembler generate pi, avoiding the gas bug. llvm-svn: 118356
* rework the rotate-by-1 instructions to be defined like theChris Lattner2010-11-063-25/+46
| | | | | | | | | | | | | shift-by-1 instructions, where the asmstring doesn't contain the implicit 1. It turns out that a bunch of these rotate instructions were completely broken because they used 1 instead of $1. This fixes assembly mismatches on "rclb $1, %bl" and friends, where we used to generate the 3 byte form, we now generate the proper 2-byte form. llvm-svn: 118355
* change the fp comparison instructions to not have %st0 explicitlyChris Lattner2010-11-062-12/+9
| | | | | | | listed in its asm string, for consistency with the other similar instructions. llvm-svn: 118354
* move the plethora of fp stack aliases to the .td file.Chris Lattner2010-11-062-39/+48
| | | | llvm-svn: 118353
* add (and document) the ability for alias results to haveChris Lattner2010-11-062-13/+16
| | | | | | | | fixed physical registers. Start moving fp comparison aliases to the .td file (which default to using %st1 if nothing is specified). llvm-svn: 118352
* Add a RegList (register list) object to ARMOperand. It will be used soon to holdBill Wendling2010-11-061-1/+38
| | | | | | | (surprise!) a list of registers. Register lists are consecutive, so we only need to record the start register plus the number of registers. llvm-svn: 118351
* generalize alias support to allow the result of an alias toChris Lattner2010-11-062-21/+20
| | | | | | | add fixed immediate values. Move the aad and aam aliases to use this, and document it. llvm-svn: 118350
* move fnstsw aliases to .td file, fix typoChris Lattner2010-11-062-36/+6
| | | | llvm-svn: 118349
* move in/out aliases to the .td files.Chris Lattner2010-11-062-16/+16
| | | | llvm-svn: 118348
* move sldt, imul, and movabsq aliases from c++ to .td file.Chris Lattner2010-11-062-29/+18
| | | | llvm-svn: 118347
* correct suffix matching to search for s/l/t suffixes on Chris Lattner2010-11-061-33/+31
| | | | | | | | | | | | | | | | | | | | | | | | | | floating point stack instructions instead of looking for b/w/l/q. This fixes issues where we'd accidentally match fistp to fistpl, when it is in fact an ambiguous instruction. This changes the behavior of llvm-mc to reject fstp, which was the correct fix for rdar://8456389: t.s:1:1: error: ambiguous instructions require an explicit suffix (could be 'fstps', 'fstpl', or 'fstpt') fstp (%rax) it also causes us to correctly reject fistp and fist, which addresses PR8528: t.s:2:1: error: ambiguous instructions require an explicit suffix (could be 'fistps', or 'fistpl') fistp (%rax) ^ t.s:3:1: error: ambiguous instructions require an explicit suffix (could be 'fists', or 'fistl') fist (%rax) ^ Thanks to Ismail Donmez for tracking down the issue here! llvm-svn: 118346
* Prune includes.Benjamin Kramer2010-11-063-7/+7
| | | | llvm-svn: 118342
* Fix grammar.Bill Wendling2010-11-061-1/+1
| | | | llvm-svn: 118341
* Fix grammar.Bill Wendling2010-11-061-3/+3
| | | | llvm-svn: 118340
* MatchRegisterName() returns 0 if it can't match the register.Bill Wendling2010-11-061-2/+2
| | | | llvm-svn: 118339
* Use TryParseRegister() instead of MatchRegisterName(). The former returns -1Bill Wendling2010-11-061-5/+2
| | | | | | while the latter doesn't. llvm-svn: 118338
* Add a note.Benjamin Kramer2010-11-061-0/+12
| | | | llvm-svn: 118337
* fix a bug where we had an implicit assumption that theChris Lattner2010-11-062-27/+14
| | | | | | | | result instruction operand numbering matched the result pattern. Fixing this allows us to move the xchg/test aliases to the .td file. llvm-svn: 118334
* Make sure we have movw on the target before using it.Eric Christopher2010-11-061-1/+1
| | | | | | Fixes 8559. llvm-svn: 118333
* move the lcall/ljmp aliases to the .td file.Chris Lattner2010-11-062-33/+20
| | | | llvm-svn: 118332
* move the "movsd -> movsl" alias to the .td files, Chris Lattner2010-11-062-36/+17
| | | | | | tidy up the movsx and movzx aliases. llvm-svn: 118331
* fix some bugs in the alias support, unblocking changing of "clr" aliasesChris Lattner2010-11-062-11/+6
| | | | | | from c++ hacks to proper .td InstAlias definitions. Change them! llvm-svn: 118330
* Reimplement BuildResultOperands to be in terms of the result instruction'sChris Lattner2010-11-061-26/+13
| | | | | | | | | | | | | | | | | | operand list instead of the operand list redundantly declared on the alias or instruction. With this change, we finally remove the ins/outs list on the alias. Before: def : InstAlias<(outs GR16:$dst), (ins GR8 :$src), "movsx $src, $dst", (MOVSX16rr8W GR16:$dst, GR8:$src)>; After: def : InstAlias<"movsx $src, $dst", (MOVSX16rr8W GR16:$dst, GR8:$src)>; This also makes the alias mechanism more general and powerful, which will be exploited in subsequent patches. llvm-svn: 118329
* Hook up the '.code {16|32}' directive to the streamer.Jim Grosbach2010-11-051-2/+5
| | | | llvm-svn: 118310
* Add '.code 32' assembler directive to MC streamers.Jim Grosbach2010-11-053-0/+3
| | | | llvm-svn: 118309
* Hook up the '.thumb_func' directive to the streamer.Jim Grosbach2010-11-051-3/+5
| | | | llvm-svn: 118307
* Fix past-o.Jim Grosbach2010-11-051-1/+1
| | | | llvm-svn: 118304
* MC'ize the '.code 16' and '.thumb_func' ARM directives.Jim Grosbach2010-11-057-13/+38
| | | | llvm-svn: 118301
* Disallow the certain NEON modified-immediate forms when generating vorr or vbic.Owen Anderson2010-11-052-7/+21
| | | | llvm-svn: 118300
* MC'ize simple ARMConstantValue entry emission (with a FIXME).Jim Grosbach2010-11-051-28/+37
| | | | llvm-svn: 118295
* Put class into an anonymous namespace.Benjamin Kramer2010-11-051-0/+2
| | | | llvm-svn: 118294
* Add codegen and encoding support for the immediate form of vbic.Owen Anderson2010-11-053-6/+78
| | | | llvm-svn: 118291
* Enable MachO writing for ARM/Darwin. Lots of stuff still doesn't workJim Grosbach2010-11-051-1/+0
| | | | | | (relocations, e.g.), but this will allow simple things to flow through. llvm-svn: 118289
* Allow targets to specify the MachO CPUType/CPUSubtype information.Jim Grosbach2010-11-053-10/+22
| | | | llvm-svn: 118288
* syntaxunified directive is a no-op for MachO writing.Jim Grosbach2010-11-051-0/+1
| | | | llvm-svn: 118287
* Add FIXME.Jim Grosbach2010-11-051-0/+1
| | | | llvm-svn: 118280
* When passing a parameter using the 'byval' mechanism, inline code needs to ↵Duncan Sands2010-11-051-0/+2
| | | | | | | | | | | | | be used to perform the copy, which may be of lots of memory [*]. It would be good if the fall-back code generated something reasonable, i.e. did the copy in a loop, rather than vast numbers of loads and stores. Add a note about this. Currently target specific code seems to always kick in so this is more of a theoretical issue rather than a practical one now that X86 has been fixed. [*] It's amazing how often people pass mega-byte long arrays by copy... llvm-svn: 118275
* CrashRecoveryContext: Add RunSafelyOnThread helper function.Daniel Dunbar2010-11-051-0/+23
| | | | llvm-svn: 118272
* When passing a huge parameter using the byval mechanism, a longDuncan Sands2010-11-041-7/+17
| | | | | | | | | sequence of loads and stores was being generated to perform the copy on the x86 targets if the parameter was less than 4 byte aligned, causing llc to use up vast amounts of memory and time. Use a "rep movs" form instead. PR7170. llvm-svn: 118260
* Use arrays instead of constant-sized SmallVectors.Benjamin Kramer2010-11-041-132/+143
| | | | llvm-svn: 118257
* Add 118023 back, but with proper spelling for .uleb128/.sleb128.Rafael Espindola2010-11-042-9/+10
| | | | llvm-svn: 118254
* Revert previous patch. Some targets don't support uleb and sayRafael Espindola2010-11-041-6/+7
| | | | | | they do :-( llvm-svn: 118250
OpenPOWER on IntegriCloud