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* PR9446: RecursivelyDeleteTriviallyDeadInstructions can delete the instructionEli Friedman2011-04-021-1/+4
| | | | | | | | | | | after the given instruction; make sure to handle that case correctly. (It's difficult to trigger; the included testcase involves a dead block, but I don't think that's a requirement.) While I'm here, get rid of the unnecessary warning about SimplifyInstructionsInBlock, since it should work correctly as far as I know. llvm-svn: 128782
* Don't assume something which might be a constant expression is an instruction.Eli Friedman2011-04-021-3/+3
| | | | | | | Based on PR9429, but no testcase because I can't figure out how to trigger it anymore given other changes to the relevant code. llvm-svn: 128781
* While SimplifyDemandedBits constant folds this, we can't rely on it here.Benjamin Kramer2011-04-021-2/+7
| | | | | | | | | | It's possible to craft an input that hits the recursion limits in a way that SimplifyDemandedBits doesn't simplify the icmp but ComputeMaskedBits can infer which bits are zero. No test case as it depends on too many other things. Fixes PR9609. llvm-svn: 128777
* ptx: support setp's 4-operand formatChe-Liang Chiou2011-04-022-35/+86
| | | | llvm-svn: 128767
* Use InterferenceCache in RegAllocGreedy.Jakob Stoklund Olesen2011-04-021-94/+46
| | | | llvm-svn: 128765
* Add an InterferenceCache class for caching per-block interference ranges.Jakob Stoklund Olesen2011-04-024-1/+300
| | | | | | | | When the greedy register allocator is splitting multiple global live ranges, it tends to look at the same interference data many times. The InterferenceCache class caches queries for unaltered LiveIntervalUnions. llvm-svn: 128764
* Use basic block numbers as indexes when mapping slot index ranges.Jakob Stoklund Olesen2011-04-021-11/+9
| | | | | | This is more compact and faster than using DenseMap. llvm-svn: 128763
* Do some peephole optimizations to remove pointless VMOVs from Neon to integerCameron Zwarich2011-04-021-0/+31
| | | | | | | | registers that arise from argument shuffling with the soft float ABI. These instructions are particularly slow on Cortex A8. This fixes one half of <rdar://problem/8674845>. llvm-svn: 128759
* Add a RemoveFromWorklist method to DCI. This is needed to do some complicatedCameron Zwarich2011-04-021-0/+4
| | | | | | | | transformations in target-specific DAG combines without causing DAGCombiner to delete the same node twice. If you know of a better way to avoid this (see my next patch for an example), please let me know. llvm-svn: 128758
* Fixed a bug in disassembly of STR_POST, where the immediate is the second ↵Johnny Chen2011-04-021-5/+13
| | | | | | | | | | operand in am2offset; instead of the second operand in addrmode_imm12. rdar://problem/9225289 llvm-svn: 128757
* Undo changes mistakenly made in revision 128750.Akira Hatanaka2011-04-022-27/+59
| | | | llvm-svn: 128751
* Insert space before ';' to prevent warnings.Akira Hatanaka2011-04-023-60/+28
| | | | llvm-svn: 128750
* Fixed MOVr for "should be" encoding bits for Inst{19-16} = 0b0000.Johnny Chen2011-04-011-0/+1
| | | | | | rdar://problem/9224276 llvm-svn: 128749
* MOVs should have Inst{19-16} as 0b0000, otherwise, the instruction is ↵Johnny Chen2011-04-011-0/+1
| | | | | | | | UNPREDICTABLE. rdar://problem/9224120 llvm-svn: 128748
* Fix the instruction table entries for AI1_adde_sube_s_irs multiclass ↵Johnny Chen2011-04-011-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | definition so that all the instruction have: let Inst{31-27} = 0b1110; // non-predicated Before, the ARM decoder was confusing: > 0x40 0xf3 0xb8 0x80 as: Opcode=16 Name=ADCSSrs Format=ARM_FORMAT_DPSOREGFRM(5) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ------------------------------------------------------------------------------------------------- | 1: 0: 0: 0| 0: 0: 0: 0| 1: 0: 1: 1| 1: 0: 0: 0| 1: 1: 1: 1| 0: 0: 1: 1| 0: 1: 0: 0| 0: 0: 0: 0| ------------------------------------------------------------------------------------------------- adcs pc, r8, r0, asr #6 since the cond field for ADCSSrs is a wild card, and so is ADCrs, with the ADCSSrs having Inst{20} as '1'. Now, the AR decoder behaves correctly: > 0x40 0xf3 0xb8 0x80 > END Executing command: /Volumes/data/lldb/llvm/Debug+Asserts/bin/llvm-mc -disassemble -triple=arm-apple-darwin -debug-only=arm-disassembler mc-input.txt Opcode=19 Name=ADCrs Format=ARM_FORMAT_DPSOREGFRM(5) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ------------------------------------------------------------------------------------------------- | 1: 0: 0: 0| 0: 0: 0: 0| 1: 0: 1: 1| 1: 0: 0: 0| 1: 1: 1: 1| 0: 0: 1: 1| 0: 1: 0: 0| 0: 0: 0: 0| ------------------------------------------------------------------------------------------------- adcshi pc, r8, r0, asr #6 > rdar://problem/9223094 llvm-svn: 128746
* Fix comment.Benjamin Kramer2011-04-011-2/+2
| | | | llvm-svn: 128745
* Tweaks to the icmp+sext-to-shifts optimization to address Frits' comments:Benjamin Kramer2011-04-011-6/+6
| | | | | | | | | | - Localize the check if an icmp has one use to a place where we know we're introducing something that's likely more expensive than a sext from i1. - Add an assert to make sure a case that would lead to a miscompilation is folded away earlier. - Fix a typo. llvm-svn: 128744
* Avoid de-referencing pass beginning of a basic block. No small test case ↵Evan Cheng2011-04-011-18/+21
| | | | | | possible. rdar://9216009 llvm-svn: 128743
* Remove redundant code. There are assignments to variables Base and Offset ↵Akira Hatanaka2011-04-011-5/+0
| | | | | | right after the code that is removed. llvm-svn: 128742
* Simplifies logic for printing target flags.Akira Hatanaka2011-04-013-34/+29
| | | | llvm-svn: 128741
* When the architecture is explicitly armv6 or thumbv6, we need to mark the ↵Owen Anderson2011-04-011-9/+15
| | | | | | object file appropriately. llvm-svn: 128739
* LDRD/STRD instructions should print both Rt and Rt2 in the asm string.Jim Grosbach2011-04-011-10/+5
| | | | llvm-svn: 128736
* Fix a LDRT/LDRBT decoding bug where for Encoding A2, if Inst{4} != 0, we ↵Johnny Chen2011-04-011-0/+8
| | | | | | | | should reject the instruction as invalid. llvm-svn: 128734
* Fix build.Benjamin Kramer2011-04-011-1/+2
| | | | llvm-svn: 128733
* InstCombine: Turn icmp + sext into bitwise/integer ops when the input has ↵Benjamin Kramer2011-04-011-0/+50
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | only one unknown bit. int test1(unsigned x) { return (x&8) ? 0 : -1; } int test3(unsigned x) { return (x&8) ? -1 : 0; } before (x86_64): _test1: andl $8, %edi cmpl $1, %edi sbbl %eax, %eax ret _test3: andl $8, %edi cmpl $1, %edi sbbl %eax, %eax notl %eax ret after: _test1: shrl $3, %edi andl $1, %edi leal -1(%rdi), %eax ret _test3: shll $28, %edi movl %edi, %eax sarl $31, %eax ret llvm-svn: 128732
* InstCombine: Move (sext icmp) transforms into their own method. No intended ↵Benjamin Kramer2011-04-012-37/+43
| | | | | | functionality change. llvm-svn: 128731
* Add comments.Evan Cheng2011-04-011-2/+4
| | | | llvm-svn: 128730
* Assign node order numbers to results of call instruction lowering. This ↵Evan Cheng2011-04-011-4/+8
| | | | | | should improve src line debug info when sdisel is used. rdar://9199118 llvm-svn: 128728
* Modifies MipsAsmPrinter::isBlockOnlyReachableByFallthrough so that it ↵Akira Hatanaka2011-04-011-1/+26
| | | | | | handles delay slots correctly. llvm-svn: 128724
* Fix LDRi12 immediate operand, which was changed to be the second operand in ↵Johnny Chen2011-04-011-3/+4
| | | | | | | | $addrmode_imm12 => (ops GPR:$base, i32imm:$offsimm). rdar://problem/9219356 llvm-svn: 128722
* Add code for analyzing FP branches. Clean up branch Analysis functions.Akira Hatanaka2011-04-012-223/+138
| | | | llvm-svn: 128718
* Initialize HasVMLxForwarding.Benjamin Kramer2011-04-011-0/+1
| | | | llvm-svn: 128709
* Various Instructions' resizeOperands() methods are only used to grow theJay Foad2011-04-011-54/+16
| | | | | | list of operands. Simplify and rename them accordingly. llvm-svn: 128708
* While testing dragonegg I noticed that isCastable and getCastOpcodeDuncan Sands2011-04-011-4/+12
| | | | | | | | had gotten out of sync: isCastable didn't think it was possible to cast the x86_mmx type to anything, while it did think it possible to cast an i64 to x86_mmx. llvm-svn: 128705
* Issue libcalls __udivmod*i4 / __divmod*i4 for div / rem pairs.Evan Cheng2011-04-013-19/+164
| | | | | | rdar://8911343 llvm-svn: 128696
* Remove unused variablesMatt Beaumont-Gay2011-04-011-3/+1
| | | | llvm-svn: 128692
* Apply again changes to support ARM memory asm parsing. I removedBruno Cardoso Lopes2011-03-319-76/+329
| | | | | | | | | | | | | | all LDR/STR changes and left them to a future patch. Passing all checks now. - Implement asm parsing support for LDRT, LDRBT, STRT, STRBT and fix the encoding wherever is possible. - Add a new encoding bit to describe the index mode used and teach printAddrMode2Operand to check by the addressing mode which index mode to print. - Testcases llvm-svn: 128689
* The basic register allocator must also use the inline spiller.Jakob Stoklund Olesen2011-03-311-1/+1
| | | | | | | It is using a trivial rewriter that doesn't know how to insert spill code requested by the standard spiller. llvm-svn: 128688
* Provide a legal pointer register class when targeting thumb1.Jakob Stoklund Olesen2011-03-312-0/+7
| | | | | | The LocalStackSlotAllocation pass was creating illegal registers. llvm-svn: 128687
* Instcombile optimization: extractelement(cast) -> cast(extractelement)Nadav Rotem2011-03-311-1/+9
| | | | llvm-svn: 128683
* InstCombine: APFloat can't perform arithmetic on PPC double doubles, don't ↵Benjamin Kramer2011-03-311-2/+4
| | | | | | | | even try. Thanks Eli! llvm-svn: 128676
* Distribute (A + B) * C to (A * C) + (B * C) to make use of NEON multiplierEvan Cheng2011-03-313-3/+53
| | | | | | | | | | | accumulator forwarding: vadd d3, d0, d1 vmul d3, d3, d2 => vmul d3, d0, d2 vmla d3, d1, d2 llvm-svn: 128665
* Fix single word and unsigned byte data transfer instruction encodings so thatJohnny Chen2011-03-311-0/+2
| | | | | | | | Inst{4} = 0. rdar://problem/9213022 llvm-svn: 128662
* Added support for FP conditional move instructions and fixed bugs in ↵Akira Hatanaka2011-03-317-285/+377
| | | | | | handling of FP comparisons. llvm-svn: 128650
* Don't completely eliminate identity copies that also modify super register ↵Jakob Stoklund Olesen2011-03-311-6/+12
| | | | | | | | | liveness. Turn them into noop KILL instructions instead. This lets the scavenger know when super-registers are killed and defined. llvm-svn: 128645
* Add BLXi to the instruction table for disassembly purpose.Johnny Chen2011-03-312-2/+23
| | | | | | | | A8.6.23 BLX (immediate) rdar://problem/9212921 llvm-svn: 128644
* Allow kill flags on two-address instructions. They are harmless.Jakob Stoklund Olesen2011-03-311-6/+2
| | | | llvm-svn: 128643
* Mark all uses as <undef> when joining a copy.Jakob Stoklund Olesen2011-03-313-8/+20
| | | | | | | | | | | | This way, shrinkToUses() will ignore the instruction that is about to be deleted, and we avoid leaving invalid live ranges that SplitKit doesn't like. Fix a misunderstanding in MachineVerifier about <def,undef> operands. The <undef> flag is valid on def operands where it has the same meaning as <undef> on a use operand. It only applies to sub-register defines which also read the full register. llvm-svn: 128642
* Remove dead code.Devang Patel2011-03-311-5/+1
| | | | llvm-svn: 128639
* Revert r128632 again, until I figure out what break the testsBruno Cardoso Lopes2011-03-319-322/+87
| | | | llvm-svn: 128635
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