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* Prevent ARM DAG Combiner from doing an AND or OR combine on an illegal ↵Tanya Lattner2011-04-071-0/+6
| | | | | | vector type (vectors of size 3). Also included test cases. llvm-svn: 129074
* Fixed a bug where missing EDInstInfo would causeSean Callanan2011-04-071-0/+3
| | | | | | tokenization to crash and burn. llvm-svn: 129051
* Sanity check MSRi for invalid mask values and reject it as invalid.Johnny Chen2011-04-071-0/+5
| | | | | | rdar://problem/9246844 llvm-svn: 129050
* PR9634: Don't unconditionally tell the AliasSetTracker that the PreheaderLoadEli Friedman2011-04-071-21/+4
| | | | | | | | | | | is equivalent to any other relevant value; it isn't true in general. If it is equivalent, the LoopPromoter will tell the AST the equivalence. Also, delete the PreheaderLoad if it is unused. Chris, since you were the last one to make major changes here, can you check that this is sane? llvm-svn: 129049
* The ARM disassembler was not recognizing USADA8 instruction. Need to add ↵Johnny Chen2011-04-071-3/+5
| | | | | | | | | | checking for register values for USAD8 and USADA8. rdar://problem/9247060 llvm-svn: 129047
* Change -arm-divmod-libcall to a target neutral option.Evan Cheng2011-04-072-6/+7
| | | | llvm-svn: 129045
* Remove dead code. rdar://9221736.Evan Cheng2011-04-071-5/+0
| | | | llvm-svn: 129044
* Should also check SMLAD for invalid register values.Johnny Chen2011-04-071-6/+12
| | | | | | rdar://problem/9246650 llvm-svn: 129042
* Simplify. isIdenticalToWhenDefined() checks opcode.Devang Patel2011-04-071-4/+2
| | | | llvm-svn: 129041
* Set unnamed_addr on strings created through the IRBuilder.Nick Lewycky2011-04-071-0/+1
| | | | llvm-svn: 129040
* Teach the ARM peephole optimizer that RSB, RSC, ADC, and SBC can be used for ↵Owen Anderson2011-04-061-1/+8
| | | | | | folded comparisons, just like ADD and SUB. llvm-svn: 129038
* Cleanups from Jim: remove redundant constraints and a dead FIXME.Owen Anderson2011-04-061-11/+5
| | | | llvm-svn: 129036
* While folding branch to a common destination into a predecessor, copy dbg ↵Devang Patel2011-04-061-4/+17
| | | | | | values also. llvm-svn: 129035
* Tidy up.Jim Grosbach2011-04-061-2/+1
| | | | llvm-svn: 129034
* A8.6.393Johnny Chen2011-04-061-26/+47
| | | | | | | | | | | | | | | | | | | | | | | | | | The ARM disassembler should reject invalid (type, align) encodings as invalid instructions. So, instead of: Opcode=1641 Name=VST2b32_UPD Format=ARM_FORMAT_NLdSt(30) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ------------------------------------------------------------------------------------------------- | 1: 1: 1: 1| 0: 1: 0: 0| 0: 0: 0: 0| 0: 0: 1: 1| 0: 0: 0: 0| 1: 0: 0: 1| 1: 0: 1: 1| 0: 0: 1: 1| ------------------------------------------------------------------------------------------------- vst2.32 {d0, d2}, [r3, :256], r3 we now have: Opcode=1641 Name=VST2b32_UPD Format=ARM_FORMAT_NLdSt(30) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ------------------------------------------------------------------------------------------------- | 1: 1: 1: 1| 0: 1: 0: 0| 0: 0: 0: 0| 0: 0: 1: 1| 0: 0: 0: 0| 1: 0: 0: 1| 1: 0: 1: 1| 0: 0: 1: 1| ------------------------------------------------------------------------------------------------- mc-input.txt:1:1: warning: invalid instruction encoding 0xb3 0x9 0x3 0xf4 ^ llvm-svn: 129033
* tidy up.Jim Grosbach2011-04-061-1/+1
| | | | llvm-svn: 129032
* Also account for the spill code that would be inserted in live-through ↵Jakob Stoklund Olesen2011-04-061-5/+16
| | | | | | blocks with interference. llvm-svn: 129030
* Abort the constraint calculation early when all positive bias is lost.Jakob Stoklund Olesen2011-04-061-33/+63
| | | | | | | Without any positive bias, there is nothing for the spill placer to to. It will spill everywhere. llvm-svn: 129029
* A8.6.92 MCR (Encoding A1): if coproc == '101x' then SEE "Advanced SIMD and VFP"Johnny Chen2011-04-061-1/+14
| | | | | | | | | | Since these "Advanced SIMD and VFP" instructions have more specfic encoding bits specified, if coproc == 10 or 11, we should reject the insn as invalid. rdar://problem/9239922 rdar://problem/9239596 llvm-svn: 129027
* Fix comment to use llvm 2.x syntax.Nick Lewycky2011-04-061-1/+1
| | | | llvm-svn: 129025
* Replace const std::vector& with ArrayRef in the type creation APIs.Nick Lewycky2011-04-062-8/+10
| | | | llvm-svn: 129024
* Keep track of the number of positively biased nodes when adding constraints.Jakob Stoklund Olesen2011-04-063-3/+16
| | | | | | If there are no positive nodes, the algorithm can be aborted early. llvm-svn: 129021
* Break the spill placement algorithm into three parts: prepare, ↵Jakob Stoklund Olesen2011-04-063-30/+39
| | | | | | | | addConstraints, and finish. This will allow us to abort the algorithm early if it is determined to be futile. llvm-svn: 129020
* Fix a bug in the disassembly of VGETLNs8 where the lane index was wrong.Johnny Chen2011-04-062-1/+3
| | | | | | | | | Also set the encoding bits (for A8.6.303, A8.6.328, A8.6.329) Inst{3-0} = 0b0000, in class NVLaneOp. rdar://problem/9240648 llvm-svn: 129015
* Add another case we are not optimizing.Rafael Espindola2011-04-061-0/+30
| | | | llvm-svn: 129012
* The original issue has been fixed by not doing unnecessary sign extensions.Rafael Espindola2011-04-061-14/+17
| | | | | | Change the test to force a sign extension and expose the problem again. llvm-svn: 129011
* face+palmDevang Patel2011-04-061-4/+4
| | | | | | Keep track of llvm.dbg.value intrinsics with non null values. llvm-svn: 129010
* Do a topological sort of the types before writing them out.Rafael Espindola2011-04-063-29/+71
| | | | | | This takes the linking of libxul on linux from 6m54.931s to 5m39.840s. llvm-svn: 129009
* Fix a few instances of "warning: extra ';' outside of a function [-pedantic]".Frits van Bommel2011-04-061-7/+7
| | | | llvm-svn: 129002
* Add an empty key for DebugLoc so that you can store an empty DebugLoc in aNick Lewycky2011-04-061-1/+1
| | | | | | DenseMap. llvm-svn: 128994
* Support using DebugLoc's in a DenseMap.Nick Lewycky2011-04-061-0/+24
| | | | llvm-svn: 128988
* Oops. Scary.Jakob Stoklund Olesen2011-04-061-1/+1
| | | | llvm-svn: 128986
* Analyze blocks with uses separately from live-through blocks without uses.Jakob Stoklund Olesen2011-04-063-89/+120
| | | | | | | | About 90% of the relevant blocks are live-through without uses, and the only information required about them is their number. This saves memory and enables later optimizations that need to look at only the use-blocks. llvm-svn: 128985
* Add a missing opcode (SMLSLDX) to BadRegsMulFrm() function.Johnny Chen2011-04-061-7/+3
| | | | | | | | | | Add more complete sanity check for LdStFrm instructions where if IBit (Inst{25}) is 1, Inst{4} should be 0. Otherwise, we should reject the insn as invalid. rdar://problem/9239347 rdar://problem/9239467 llvm-svn: 128977
* RuntimeDyld should use the memory manager API.Jim Grosbach2011-04-062-91/+88
| | | | | | | | | | Start teaching the runtime Dyld interface to use the memory manager API for allocating space. Rather than mapping directly into the MachO object, we extract the payload for each object and copy it into a dedicated buffer allocated via the memory manager. For now, just do Segment64, so this works on x86_64, but not yet on ARM. llvm-svn: 128973
* Reapply r128946 (pseudoization of various instructions), and fix the extra ↵Owen Anderson2011-04-052-65/+42
| | | | | | imp-def of CPSR it was adding. llvm-svn: 128965
* Make the virtual destructor out-of-line so we have a key function.Chandler Carruth2011-04-051-0/+3
| | | | llvm-svn: 128964
* Sign errorJakob Stoklund Olesen2011-04-051-1/+1
| | | | llvm-svn: 128963
* Don't crash when a value is defined after the last split point.Jakob Stoklund Olesen2011-04-051-1/+2
| | | | llvm-svn: 128962
* Permit blocks to branch directly to a landing pad.Jakob Stoklund Olesen2011-04-051-0/+5
| | | | | | Treat the landing pad as a normal successor when that happens. llvm-svn: 128961
* Remove extraneous 'return'.Jim Grosbach2011-04-051-2/+1
| | | | llvm-svn: 128959
* Fix a typo in the handling of PKHTB opcode, plus add sanity check for ↵Johnny Chen2011-04-051-1/+7
| | | | | | | | | | illegal register encodings for DisassembleArithMiscFrm(). rdar://problem/9238659 llvm-svn: 128958
* Clean up some code for clarity.Bob Wilson2011-04-051-5/+24
| | | | llvm-svn: 128953
* Revert r128946 while I figure out why it broke the buildbots.Owen Anderson2011-04-052-38/+64
| | | | llvm-svn: 128951
* A7.3 register encodingJohnny Chen2011-04-051-0/+10
| | | | | | | | | | | | | Qd -> bit[12] == 0 Qn -> bit[16] == 0 Qm -> bit[0] == 0 If one of these bits is 1, the instruction is UNDEFINED. rdar://problem/9238399 rdar://problem/9238445 llvm-svn: 128949
* Add support to encode function's template parameters.Devang Patel2011-04-052-4/+11
| | | | llvm-svn: 128947
* Give RSBS and RSCS the pseudo treatment.Owen Anderson2011-04-052-64/+38
| | | | llvm-svn: 128946
* ARM disassembler was erroneously accepting an invalid RSC instruction.Johnny Chen2011-04-051-0/+6
| | | | | | | | Added checks for regs which should not be 15. rdar://problem/9237734 llvm-svn: 128945
* remove postdom frontiers, because it is dead. Forward dom frontiers areChris Lattner2011-04-052-52/+0
| | | | | | still used by RegionInfo :( llvm-svn: 128943
* ARM disassembler was erroneously accepting an invalid LSL instruction.Johnny Chen2011-04-051-0/+4
| | | | | | | | | For register-controlled shifts, we should check that the encoding constraint Inst{7} = 0 and Inst{4} = 1 is satisfied. rdar://problem/9237693 llvm-svn: 128941
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