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* Realign BLEND patterns to match the general style for patterns in .td file.Bruno Cardoso Lopes2011-09-121-45/+42
| | | | llvm-svn: 139526
* Fix 80-columnsBruno Cardoso Lopes2011-09-121-12/+16
| | | | llvm-svn: 139525
* Port more encoding tests to decoding tests, and correct an improper Thumb2 ↵Owen Anderson2011-09-122-0/+36
| | | | | | pre-indexed load decoding this uncovered. llvm-svn: 139522
* Rename -disable-iv-rewrite to -enable-iv-rewrite=false in preparation for ↵Andrew Trick2011-09-121-42/+20
| | | | | | default change. llvm-svn: 139517
* Add asserts to keep front-ends honest while encoding debug info into LLVM IR ↵Devang Patel2011-09-121-0/+9
| | | | | | using DIBuilder. llvm-svn: 139515
* Add DW_ATE_UTF, which clang started using in my previous commit!Devang Patel2011-09-121-0/+1
| | | | llvm-svn: 139503
* Remove the -compact-regions flag.Jakob Stoklund Olesen2011-09-121-11/+5
| | | | | | | It has been enabled by default for a while, it was only there to allow performance comparisons. llvm-svn: 139501
* Add an interface for SplitKit complement spill modes.Jakob Stoklund Olesen2011-09-123-5/+49
| | | | | | | | | | | | | | | | | | | | | | | | | SplitKit always computes a complement live range to cover the places where the original live range was live, but no explicit region has been allocated. Currently, the complement live range is created to be as small as possible - it never overlaps any of the regions. This minimizes register pressure, but if the complement is going to be spilled anyway, that is not very important. The spiller will eliminate redundant spills, and hoist others by making the spill slot live range overlap some of the regions created by splitting. Stack slots are cheap. This patch adds the interface to enable spill modes in SplitKit. In spill mode, SplitKit will assume that the complement is going to spill, so it will allow it to overlap regions in order to avoid back-copies. By doing some of the spiller's work early, the complement live range becomes simpler. In some cases, it can become much simpler because no extra PHI-defs are required. This will speed up both splitting and spilling. This is only the interface to enable spill modes, no implementation yet. llvm-svn: 139500
* Update comments to reflect some (not so) recent changes.Jakob Stoklund Olesen2011-09-121-4/+5
| | | | llvm-svn: 139498
* Associate a MemOperand with LDWCP nodes introduced during ISel.Richard Osborne2011-09-121-3/+8
| | | | | | This information is required if we want LDWCP to be hoisted out of loops. llvm-svn: 139495
* Mark LDWCP as having no side effects.Richard Osborne2011-09-121-1/+1
| | | | llvm-svn: 139494
* Format patterns, remove unused X86blend patternsNadav Rotem2011-09-122-27/+34
| | | | llvm-svn: 139491
* Fix disassembling of one of the register/register forms of ↵Craig Topper2011-09-111-0/+62
| | | | | | MOVUPS/MOVUPD/MOVAPS/MOVAPD/MOVSS/MOVSD and their VEX equivalents. Fixes PR10877. llvm-svn: 139486
* Fix disassembling of reverse register/register forms of ↵Craig Topper2011-09-111-4/+13
| | | | | | ADD/SUB/XOR/OR/AND/SBB/ADC/CMP/MOV. llvm-svn: 139485
* CR fixes per Bruno's request.Nadav Rotem2011-09-113-94/+48
| | | | | | | Undo the changes from r139285 which added custom lowering to vselect. Add tablegen lowering for vselect. llvm-svn: 139479
* r139454 activates an assert in a case where we were doing the right thing ↵Eli Friedman2011-09-101-1/+9
| | | | | | anyway. Make that explicit, and un-XFAIL the testcase. llvm-svn: 139458
* Fix the asserts in lib/Target/X86/X86ELFWriterInfo.cpp andRichard Trieu2011-09-102-2/+2
| | | | | | | | | | | | lib/ExecutionEngine/MCJIT/MCJIT.cpp from: assert("error"); to: assert(0 && "error"); llvm-svn: 139456
* Fixed an assert from:Richard Trieu2011-09-101-1/+1
| | | | | | | | | | | | | | assert("not implemented for target shuffle node"); to: assert(0 && "not implemented for target shuffle node"); This causes a test failure in CodeGen/X86/palignr.ll which has been marked as XFAIL for the time being. Test failure filed at PR10901. llvm-svn: 139454
* [disable-iv-rewrite] Allow WidenIV to handle NSW/NUW operationsAndrew Trick2011-09-101-1/+40
| | | | | | | | | | | | better. Don't immediately give up when an add operation can't be trivially sign/zero-extended within a loop. If it has NSW/NUW flags, generate a new expression with sign extended (non-recurrent) operand. As before, if SCEV says that all sign extends are loop invariant, then we can widen the operation. llvm-svn: 139453
* Set NSW/NUW flags on SCEVAddExpr when the operation is flagged asAndrew Trick2011-09-101-1/+7
| | | | | | | | | | such. I'm doing this now for completeness because I can't think of/remember any reason that it was left out. I'm not sure it will help anything, but if we don't do it we need to explain why in comments. llvm-svn: 139450
* Fix asserts in CodeGen from:Richard Trieu2011-09-102-3/+3
| | | | | | | | | | assert("error"); to: assert(0 && "error"); llvm-svn: 139449
* Thumb2 parsing and encoding for MOV(immediate).Jim Grosbach2011-09-102-4/+58
| | | | | | | Some aliases for MOV(register) also to keep existing T1 tests happy when run in thumbv7 mode. llvm-svn: 139440
* LDM writeback is not allowed if Rn is in the target register list.Owen Anderson2011-09-091-0/+19
| | | | llvm-svn: 139432
* Fix an ambiguously nested if.Owen Anderson2011-09-091-2/+2
| | | | llvm-svn: 139431
* Fix buildbot breakage caused by r139415. I missed one instance of a ↵Owen Anderson2011-09-091-1/+5
| | | | | | manually create ARM::tB. llvm-svn: 139429
* Fix assembly/disassembly of Thumb2 ADR instructions with immediate operands.Owen Anderson2011-09-093-2/+27
| | | | llvm-svn: 139422
* O64 will not be supported.Akira Hatanaka2011-09-092-2/+1
| | | | llvm-svn: 139421
* Make F31 and D15 non-reserved registers.Akira Hatanaka2011-09-092-5/+1
| | | | llvm-svn: 139420
* tidy up a bitChris Lattner2011-09-091-7/+5
| | | | llvm-svn: 139419
* Thumb unconditional branches are allowed in IT blocks, and therefore should ↵Owen Anderson2011-09-099-23/+70
| | | | | | have a predicate operand, unlike conditional branches. llvm-svn: 139415
* Mips32 does not reserve even-numbered floating point registers.Akira Hatanaka2011-09-091-5/+0
| | | | llvm-svn: 139412
* Make the SelectionDAG verify that all the operands of BUILD_VECTOR have the ↵Eli Friedman2011-09-092-24/+36
| | | | | | same type. Teach DAGCombiner::visitINSERT_VECTOR_ELT not to make invalid BUILD_VECTORs. Fixes PR10897. llvm-svn: 139407
* Drop support for Mips1 and Mips2.Akira Hatanaka2011-09-099-87/+6
| | | | llvm-svn: 139405
* Implement vector-select support for avx256. Refactor the vblend ↵Nadav Rotem2011-09-094-30/+63
| | | | | | implementation to have tablegen match the instruction by the node type llvm-svn: 139400
* Thumb2 assembly parsing and encoding for MLA and MLS.Jim Grosbach2011-09-091-2/+2
| | | | llvm-svn: 139399
* Don't tack "Instruction not interpretable yet!" onto the end ofDuncan Sands2011-09-091-1/+1
| | | | | | the instruction. llvm-svn: 139398
* Thumb2 assembly parsing and encoding for LDRSB.Jim Grosbach2011-09-091-1/+11
| | | | llvm-svn: 139389
* Drop support for Allegrex. Allegrex implements a variant of Mips2.Akira Hatanaka2011-09-092-23/+0
| | | | llvm-svn: 139383
* Thumb2 assembly parsing and encoding for LDREX/LDREXB/LDREXD/LDREXH.Jim Grosbach2011-09-098-40/+125
| | | | llvm-svn: 139381
* Reapply r139247: Cache intermediate results during traceSiblingValue.Jakob Stoklund Olesen2011-09-091-82/+239
| | | | | | | | | | | | | | | | | In some cases such as interpreters using indirectbr, the CFG can be very complicated, and live range splitting may be forced to insert a large number of phi-defs. When that happens, traceSiblingValue can spend a lot of time zipping around in the CFG looking for defs and reloads. This patch causes more information to be cached in SibValues, and the cached values are used to terminate searches early. This speeds up spilling by 20x in one interpreter test case. For more typical code, this is just a 10% speedup of spilling. The previous version had bugs that caused miscompilations. They have been fixed. llvm-svn: 139378
* Comment formatting.Andrew Trick2011-09-091-15/+16
| | | | llvm-svn: 139375
* Fix handling of Intel syntax disassembling of movs and stos to stop being ↵Craig Topper2011-09-091-12/+12
| | | | | | blank. Also fixed scas, and cmps to always print size suffix in Intel syntax since its abiguous without arguments. Fixes PR10875. llvm-svn: 139353
* Change default target architecture from Mips1 to Mips32r1 in preparation forAkira Hatanaka2011-09-092-2/+2
| | | | | | | | | removing support for Mips1 and Mips2. This change and the ones that follow have been discussed with and approved by Bruno. llvm-svn: 139344
* Remove dead code.Benjamin Kramer2011-09-091-8/+0
| | | | llvm-svn: 139343
* Fix release build:Nick Lewycky2011-09-091-3/+1
| | | | | | MachOObjectFile.cpp:524: error: unused variable 'NumLoadCommands' [-Wunused-variable] llvm-svn: 139341
* 80 columns.Akira Hatanaka2011-09-093-3/+3
| | | | llvm-svn: 139339
* Directly point debug info to the stack slot of the arugment, instead of ↵Devang Patel2011-09-083-28/+25
| | | | | | trying to keep track of vreg in which it the arugment is copied. The LiveDebugVariable can keep track of variable's ranges. llvm-svn: 139330
* All conditional branches are disallowed in IT blocks, not just CBZ/CBNZ.Owen Anderson2011-09-081-2/+3
| | | | llvm-svn: 139329
* Soft fail CBZ/CBNZ in the disassembler if they appear inside an IT block.Owen Anderson2011-09-081-12/+21
| | | | llvm-svn: 139328
* Formatting and typo.Eric Christopher2011-09-081-2/+3
| | | | llvm-svn: 139325
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