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* DAGCombiner: Fold away vector extract of insert with the same indexMatt Arsenault2016-07-051-0/+8
| | | | | | | This only really matters when the index is non-constant since the constant case already gets taken care of by other combines. llvm-svn: 274569
* AArch64: use correct SDValue # when looking for bitfield placement.Tim Northover2016-07-051-2/+3
| | | | | | | | | | The other use really does only care about the SDNode (it checks the opcode against a whitelist), but bitFieldPlacement can be misled if the node produces multiple results. Patch by Ismail Badawi. llvm-svn: 274567
* AMDGPU: Fix folding SGPRs into madak/madmk src0Matt Arsenault2016-07-054-6/+26
| | | | | | | | | | Because of the special immediate operand, the constant bus is already used so SGPRs are never useful. r263212 changed the name of the immediate operand, which broke the verifier check for the restriction. llvm-svn: 274564
* [MC/Darwin] Fix a -Wmisleading-indentation warning, reported by GCC 6.Davide Italiano2016-07-051-2/+2
| | | | llvm-svn: 274563
* AMDGPU/SI: Remove address space query functions from AMDGPUDAGToDAGISelTom Stellard2016-07-053-156/+78
| | | | | | | | | | | | | | | Summary: These have been replaced with TableGen code (except for isConstantLoad, which is still used for R600). The queries were broken for cases where MemOperand was a PseudoSourceValue. Reviewers: arsenm Subscribers: arsenm, kzhuravl, llvm-commits Differential Revision: http://reviews.llvm.org/D21684 llvm-svn: 274561
* [LV] Refactor integer induction widening (NFC)Matthew Simpson2016-07-051-87/+86
| | | | | | | | | This patch also removes the SCEV variants of getStepVector() since they have no uses after the refactoring. Differential Revision: http://reviews.llvm.org/D21903 llvm-svn: 274558
* [AMDGPU] rename DS_1A1D_Off8_NORET to DS_1A2D_Off8_NORET as ds_write2xx use ↵Valery Pykhtin2016-07-052-5/+5
| | | | | | 2 source registers. NFC. llvm-svn: 274556
* [X86][AVX512] Remove vector BROADCAST builtins.Simon Pilgrim2016-07-051-34/+0
| | | | llvm-svn: 274555
* [LLVM][INTRINSICS] adding intrinsics of CLFLUSHOPTMichael Zuckerman2016-07-051-1/+1
| | | | | | Differential Revision: http://reviews.llvm.org/D21789 llvm-svn: 274553
* [AMDGPU] Assembler: Fix parsing error with floating-point literals passed to ↵Sam Kolton2016-07-051-6/+1
| | | | | | | | integer instructions Differential Revision: http://reviews.llvm.org/D21972 llvm-svn: 274551
* [X86][AVX512] Autoupgrade the BROADCAST intrinsicsSimon Pilgrim2016-07-051-1/+9
| | | | llvm-svn: 274550
* [mips][ias] Remove k_PhysReg since it's not possible to create an operand of ↵Daniel Sanders2016-07-051-20/+7
| | | | | | | | | | | | this kind. Reviewers: sdardis Subscribers: dsanders, sdardis, llvm-commits Differential Revision: http://reviews.llvm.org/D21986 llvm-svn: 274547
* [Thumb] Reapply r272251 with a fix for PR28348 (mk 2)James Molloy2016-07-051-1/+43
| | | | | | | | | | | | | | | | | | | | | | | | | The important thing I was missing was ensuring newly added constants were kept in topological order. Repositioning the node is correct if the constant is newly added (so it has no topological ordering) but wrong if it already existed - positioning it next in the worklist would break the topological ordering. Original commit message: [Thumb] Select a BIC instead of AND if the immediate can be encoded more optimally negated If an immediate is only used in an AND node, it is possible that the immediate can be more optimally materialized when negated. If this is the case, we can negate the immediate and use a BIC instead; int i(int a) { return a & 0xfffffeec; } Used to produce: ldr r1, [CONSTPOOL] ands r0, r1 CONSTPOOL: 0xfffffeec And now produces: movs r1, #255 adds r1, #20 ; Less costly immediate generation bics r0, r1 llvm-svn: 274543
* Revert r274536: [mips][ias] Don't break apart and reconstruct StringRef's ↵Daniel Sanders2016-07-051-4/+6
| | | | | | | | for k_Token. NFC. It turns out that MSVC requires this. llvm-svn: 274538
* [mips][ias] Don't break apart and reconstruct StringRef's for k_Token. NFC.Daniel Sanders2016-07-051-6/+4
| | | | llvm-svn: 274536
* [PowerPC] - Legalize vector types by widening instead of integer promotionNemanja Ivanovic2016-07-053-1/+100
| | | | | | | | | | | | | | | | | | | This patch corresponds to review: http://reviews.llvm.org/D20443 It changes the legalization strategy for illegal vector types from integer promotion to widening. This only applies for vectors with elements of width that is a multiple of a byte since we have hardware support for vectors with 1, 2, 3, 8 and 16 byte elements. Integer promotion for vectors is quite expensive on PPC due to the sequence of breaking apart the vector, extending the elements and reconstituting the vector. Two of these operations are expensive. This patch causes between minor and major improvements in performance on most benchmarks. There are very few benchmarks whose performance regresses. These regressions can be handled in a subsequent patch with a DAG combine (similar to how this patch handles int -> fp conversions of illegal vector types). llvm-svn: 274535
* Object: support empty UID/GID fieldsSaleem Abdulrasool2016-07-051-2/+8
| | | | | | | | | Normal archives do not have empty UID/GID fields. However, the Microsoft Import library format is a customized archive (it just uses an alternate symbol index format). When the import library is constructed by lib.exe, the UID and GID fields are left empty. Do not abort on such an input. llvm-svn: 274528
* AMDGPU/R600: Add PatFrags for selecting the correct vtx id for loadsTom Stellard2016-07-054-45/+65
| | | | | | | | | This moves of the r600 logic out of isGlobalLoad() and into the TableGen files. Differential Revision: http://reviews.llvm.org/D21710 llvm-svn: 274527
* [Support][Error] Make logAllUnhandledErrors take a Twine for the banner, ratherLang Hames2016-07-041-0/+9
| | | | | | than a const string&. llvm-svn: 274526
* [IR,X86] Remove some intrinsic prefixes earlier in the auto-upgrade code so ↵Craig Topper2016-07-041-214/+226
| | | | | | we can shorten the length of the comparison strings and avoid repeatedly comparing the common prefix. No functional change intended. llvm-svn: 274522
* AMDGPU/SI: Remove hack for selecting < 32-bit loads to MUBUF instructionsTom Stellard2016-07-043-15/+15
| | | | | | | | | | | | | | | Summary: The isGlobalLoad() query was returning true for constant address space loads with memory types less than 32-bits, which is wrong. This logic has been replaced with PatFrag in the TableGen files, to provide the same functionality. Reviewers: arsenm Subscribers: arsenm, kzhuravl, llvm-commits Differential Revision: http://reviews.llvm.org/D21696 llvm-svn: 274521
* [X86][AVX512] Add support for lowering shuffles to VSHUFPDSimon Pilgrim2016-07-041-0/+5
| | | | llvm-svn: 274520
* [AVX512] Remove masked VPERMD/VPERMQ/VPERMILPS/VPERMILPD intrinsics. They ↵Craig Topper2016-07-041-16/+0
| | | | | | were autoupgraded to native IR in r274506 and r274506. llvm-svn: 274519
* AMDGPU/R600: Add indentation to VTX and TEX fetch asm stringsJan Vesely2016-07-041-2/+2
| | | | | | | | These are printed as part of Fetch clauses. Differential Revision: http://reviews.llvm.org/D21730 llvm-svn: 274517
* Revert "[Thumb] Reapply r272251 with a fix for PR28348"James Molloy2016-07-041-40/+1
| | | | | | This reverts commit r274510 - it made green dragon unhappy. llvm-svn: 274512
* [Thumb] Reapply r272251 with a fix for PR28348James Molloy2016-07-041-1/+40
| | | | | | | | | | | | | | | | | | | | | | | | | We were using DAG->getConstant instead of DAG->getTargetConstant. This meant that we could inadvertently increase the use count of a constant if stars aligned, which it did in this testcase. Increasing the use count of the constant could cause ISel to fall over (because DAGToDAG lowering assumed the constant had only one use!) Original commit message: [Thumb] Select a BIC instead of AND if the immediate can be encoded more optimally negated If an immediate is only used in an AND node, it is possible that the immediate can be more optimally materialized when negated. If this is the case, we can negate the immediate and use a BIC instead; int i(int a) { return a & 0xfffffeec; } Used to produce: ldr r1, [CONSTPOOL] ands r0, r1 CONSTPOOL: 0xfffffeec And now produces: movs r1, #255 adds r1, #20 ; Less costly immediate generation bics r0, r1 llvm-svn: 274510
* [X86][AVX512] Autoupgrade the VPERMPD/VPERMQ intrinsicsSimon Pilgrim2016-07-041-0/+18
| | | | llvm-svn: 274506
* [X86][AVX512] Autoupgrade the VPERMILPD/VPERMILPS intrinsicsSimon Pilgrim2016-07-041-1/+3
| | | | llvm-svn: 274498
* Fixed warning caused by r274402.Eric Liu2016-07-041-5/+5
| | | | llvm-svn: 274497
* Add writeonly IR attributeNicolai Haehnle2016-07-049-22/+49
| | | | | | | | | | | | | | | | | Summary: This complements the earlier addition of IntrWriteMem and IntrWriteArgMem LLVM intrinsic properties, see D18291. Also start using the attribute for memset, memcpy, and memmove intrinsics, and remove their special-casing in BasicAliasAnalysis. Reviewers: reames, joker.eph Subscribers: joker.eph, llvm-commits Differential Revision: http://reviews.llvm.org/D18714 llvm-svn: 274485
* [CodeGen] Make the code that detects a if a shuffle is really a ↵Craig Topper2016-07-041-33/+41
| | | | | | | | | | concatenation of the inputs more general purpose. We can now handle concatenation of each source multiple times. The previous code just checked for each source to appear once in either order. This also now handles an entire source vector sized piece having undef indices correctly. We now concat with UNDEF instead of using one of the sources. This is responsible for the test case change. llvm-svn: 274483
* Reformat blank lines.NAKAMURA Takumi2016-07-042-11/+10
| | | | llvm-svn: 274481
* Reformat comment lines.NAKAMURA Takumi2016-07-042-9/+9
| | | | llvm-svn: 274480
* Untabify.NAKAMURA Takumi2016-07-043-6/+5
| | | | llvm-svn: 274479
* Reformat.NAKAMURA Takumi2016-07-042-32/+30
| | | | llvm-svn: 274478
* [X86] Add shuffle mask rescaling helper function. NFCI.Simon Pilgrim2016-07-031-12/+26
| | | | llvm-svn: 274476
* [X86][AVX2] Merge unary permute matching behind the same V2.isUndef() ↵Simon Pilgrim2016-07-031-9/+8
| | | | | | condition. NFCI. llvm-svn: 274474
* [X86][AVX512] Add support for 512-bit shuffle lowering to VPERMPD/VPERMQSimon Pilgrim2016-07-031-14/+39
| | | | llvm-svn: 274473
* [CodeGen] Teach OR combine of shuffles involving zero vectors to better ↵Craig Topper2016-07-031-5/+10
| | | | | | | | handle undef indices. Undef indices can now be treated as zeros. Or if its undef ORed with zero, we will keep the undef. llvm-svn: 274472
* [MBB] add a missing corner case in UpdateTerminator()Haicheng Wu2016-07-031-10/+20
| | | | | | | | | | After the block placement, if a block ends with a conditional branch, but the next block is not its successor. The conditional branch should be changed to unconditional branch. This patch fixes PR28307, PR28297, PR28402. Differential Revision: http://reviews.llvm.org/D21811 llvm-svn: 274470
* [X86][AVX512] Add support for VPERMPD/VPERMQ masked shuffle commentsSimon Pilgrim2016-07-031-0/+16
| | | | llvm-svn: 274469
* [X86][AVX512] Add support for 512-bit shuffle decoding of VPERMPD/VPERMQSimon Pilgrim2016-07-034-26/+30
| | | | llvm-svn: 274468
* [X86][AVX] Renamed VPERMILPI shuffle comment macros to be more specificSimon Pilgrim2016-07-031-27/+27
| | | | llvm-svn: 274467
* [X86][AVX512] Add support for VPALIGNR/PSHUFD/PSHUFHW/PSHUFLW masked shuffle ↵Simon Pilgrim2016-07-031-0/+16
| | | | | | comments llvm-svn: 274466
* [InstCombine] enable vector select of bools -> logic foldsSanjay Patel2016-07-031-5/+8
| | | | llvm-svn: 274465
* [X86][AVX512] Add support for UNPCK masked shuffle commentsSimon Pilgrim2016-07-031-1/+51
| | | | llvm-svn: 274464
* fix formatting; NFCSanjay Patel2016-07-031-6/+6
| | | | llvm-svn: 274463
* [X86][AVX512] Add support for VPERM/VSHUF masked shuffle commentsSimon Pilgrim2016-07-031-0/+56
| | | | llvm-svn: 274462
* [X86][AVX512] Add support for PMOVZX masked shuffle commentsSimon Pilgrim2016-07-031-0/+34
| | | | llvm-svn: 274461
* [X86][AVX512] Add support for masked shuffle commentsSimon Pilgrim2016-07-031-2/+53
| | | | | | | | | | This patch adds support for including the avx512 mask register information in the mask/maskz versions of shuffle instruction comments. This initial version just adds support for MOVDDUP/MOVSHDUP/MOVSLDUP to reduce the mass of test regenerations, other shuffle instructions can be added in due course. Differential Revision: http://reviews.llvm.org/D21953 llvm-svn: 274459
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