summaryrefslogtreecommitdiffstats
path: root/llvm/lib
Commit message (Collapse)AuthorAgeFilesLines
...
* [X86] Merge getBitTestCondition into LowerAndToBT. Don't create ↵Craig Topper2018-12-271-49/+49
| | | | | | | | | | X86ISD::SETCC node in the merged function. NFCI Only one of the 3 callers of LowerAndToBT need the SETCC node. Two of them have to look through it to find the operands they really need. Instead create it after the one call that needs it. LowerAndToBT now returns both the BT node and the X86 specific condition code separately. llvm-svn: 350081
* [WebAssembly] Added basic support for if/else/end_if in MC layer.Wouter van Oortmerssen2018-12-262-5/+12
| | | | | | | | | | | | | | | | | Summary: These instructions are currently unused in our backend, but for completeness it is good to support them, so they can be used with the assembler in hand-written code. Tests are very basic, signature support missing much like other blocks. Reviewers: dschuff, aheejin Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D55973 llvm-svn: 350079
* [WebAssembly] Make assembler check for proper nesting of control flow.Wouter van Oortmerssen2018-12-262-5/+110
| | | | | | | | | | | | | | | | | | | | | Summary: It does so using a simple nesting stack, and gives clear errors upon violation. This is unique to wasm, since most CPUs do not have any nested constructs. Had to add an end of file check to the general assembler for this. Note: if/else/end instructions are not currently supported in our tablegen defs, so these tests will be enabled in a follow-up. They already pass the nesting check. Reviewers: dschuff, aheejin Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D55797 llvm-svn: 350078
* [WebAssembly] Delete an unnecessary line in RegStackifyHeejin Ahn2018-12-261-1/+0
| | | | | | | `OneUseInst` is set outside of the loop before and `OneUse` does not change throughout the loop, so this line is not necessary. llvm-svn: 350076
* [WebAssembly] Fix typos in comments in RegStackify (NFC)Heejin Ahn2018-12-261-2/+2
| | | | llvm-svn: 350075
* [LoopIdiomRecognize] Add CTTZ supportCraig Topper2018-12-261-64/+85
| | | | | | | | | | | | | | | | | | | | | Summary: Existing LIR recognizes CTLZ where shifting input variable right until it is zero. (Shift-Until-Zero idiom) This commit: 1. Augments Shift-Until-Zero idiom to recognize CTTZ where input variable is shifted left. 2. Prepare for BitScan idiom recognition. Patch by Yuanfang Chen (tabloid.adroit) Reviewers: craig.topper, evstupac Reviewed By: craig.topper Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D55876 llvm-svn: 350074
* [codeview] Check if this 'this' type of a method is a pointerReid Kleckner2018-12-262-8/+19
| | | | | | | | | Fixes crash reported after r347354 for frontends that don't always emit 'this' pointers for methods. Now we will silently produce debug info that makes functions like this look like static methods, which seems reasonable. llvm-svn: 350073
* [NVPTX] Allow libcalls that are defined in the current module.Justin Lebar2018-12-269-4/+228
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The patch adds a possibility to make library calls on NVPTX. An important thing about library functions - they must be defined within the current module. This basically should guarantee that we produce a valid PTX assembly (without calls to not defined functions). The one who wants to use the libcalls is probably will have to link against compiler-rt or any other implementation. Currently, it's completely impossible to make library calls because of error LLVM ERROR: Cannot select: i32 = ExternalSymbol '...'. But we can lower ExternalSymbol to TargetExternalSymbol and verify if the function definition is available. Also, there was an issue with a DAG during legalisation. When we expand instruction into libcall, the inner call-chain isn't being "integrated" into outer chain. Since the last "data-flow" (call retval load) node is located in call-chain earlier than CALLSEQ_END node, the latter becomes a leaf and therefore a dead node (and is being removed quite fast). Proposed here solution relies on another data-flow pseudo nodes (ProxyReg) which purpose is only to keep CALLSEQ_END at legalisation and instruction selection phases - we remove the pseudo instructions before register scheduling phase. Patch by Denys Zariaiev! Differential Revision: https://reviews.llvm.org/D34708 llvm-svn: 350069
* [NFC] Use utility function for guards detectionMax Kazantsev2018-12-261-3/+3
| | | | llvm-svn: 350064
* [MIPS GlobalISel] Select G_SELECTPetar Avramovic2018-12-254-8/+32
| | | | | | | | | | Add widen scalar for type index 1 (i1 condition) for G_SELECT. Select G_SELECT for pointer, s32(integer) and smaller low level types on MIPS32. Differential Revision: https://reviews.llvm.org/D56001 llvm-svn: 350063
* [NFC] Reuse variables instead of re-calling getParentMax Kazantsev2018-12-251-2/+1
| | | | llvm-svn: 350062
* [PowerPC] Fix the bug of ISD::ADDE to set its second return type to glueKang Zhang2018-12-251-1/+1
| | | | | | | | | | | | | | | Summary: This patch is to fix the bug imported by rL341634. In above submit , the the return type of ISD::ADDE is 14224: SDVTList VTs = DAG.getVTList(MVT::i64, MVT::i64), but in fact, the second return type of ISD::ADDE should be MVT::Glue not MVT::i64. Reviewed By: hfinkel Differential Revision: https://reviews.llvm.org/D55977 llvm-svn: 350061
* [X86] Use GetDemandedBits to simplify the operands of PMULDQ/PMULUDQ.Craig Topper2018-12-242-0/+18
| | | | | | | | | | | | | | This is an alternative to what I attempted in D56057. GetDemandedBits is a special version of SimplifyDemandedBits that allows simplifications even when the operand has other uses. GetDemandedBits will only do simplifications that allow a node to be bypassed. It won't create new nodes or alter any of the other users. I had to add support for bypassing SIGN_EXTEND_INREG to GetDemandedBits. Based on a patch that Simon Pilgrim sent me in email. Fixes PR40142. llvm-svn: 350059
* [HWASAN] Instrument memorty intrinsics by defaultEugene Leviant2018-12-241-1/+1
| | | | | | Differential revision: https://reviews.llvm.org/D55926 llvm-svn: 350055
* Revert rL350048 and rL350050Max Kazantsev2018-12-242-16/+9
| | | | | | | These patches have broken almost all buildbots on test DebugInfo/X86/addr_comments.ll. Reverting to green. llvm-svn: 350052
* Fix build - follow-up to r350048 which broke headerless (v4) address poolDavid Blaikie2018-12-242-8/+10
| | | | llvm-svn: 350050
* [LoopSimplifyCFG] Delete dead exiting edgesMax Kazantsev2018-12-241-8/+111
| | | | | | | | | | This patch teaches LoopSimplifyCFG to remove dead exiting edges from loops. Differential Revision: https://reviews.llvm.org/D54025 Reviewed By: fedor.sergeev llvm-svn: 350049
* DebugInfo: Use assembly label arithmetic for address pool size for easier ↵David Blaikie2018-12-242-5/+10
| | | | | | reading/editing llvm-svn: 350048
* DebugInfo: Add assembly comments for debug_addr contribution header fieldsDavid Blaikie2018-12-241-0/+4
| | | | llvm-svn: 350047
* llvm-dwarfdump: Skip address index info (and dump only the address, if ↵David Blaikie2018-12-241-4/+5
| | | | | | | | found) when non-verbose dumping addrx forms There's a few bugs here still - demonstrated with FIXITs in the test. llvm-svn: 350046
* Return "[LoopSimplifyCFG] Delete dead in-loop blocks"Max Kazantsev2018-12-241-10/+32
| | | | | | | | The underlying bug that caused the revert should be fixed by rL348567. Differential Revision: https://reviews.llvm.org/D54023 llvm-svn: 350045
* [LoopIdioms] More LocationSize::precise annotations; NFCGeorge Burgess IV2018-12-242-3/+5
| | | | | | | | | Both of these places reference memset-like loops. Memset is precise. Trying to keep these patches super small so they're easily post-commit verifiable, as requested in D44748. llvm-svn: 350044
* [X86] Remove unused variables left after r350041. NFCCraig Topper2018-12-241-6/+0
| | | | llvm-svn: 350043
* [SelectionDAGBuilder] Use ::precise LocationSizes; NFCGeorge Burgess IV2018-12-241-11/+23
| | | | | | | | | | | | | | | More migration so we can disable the implicit int -> LocationSize conversion. All of these are either scatter/gather'ed vector instructions, or direct loads. Hence, they're all precise. Perhaps if we see way more getTypeStoreSize calls, we can make a getTypeStoreLocationSize (or similar) as a wrapper that applies this ::precise. Doesn't appear that it's a good idea to make getTypeStoreSize return a LocationSize itself, however. llvm-svn: 350042
* [X86] Move the optimization that turns 'CMP (AND+IMM64), 0' into ↵Craig Topper2018-12-242-55/+75
| | | | | | | | SRL/SHL+TEST to X86ISelDAGToDAG. This cleans more code out of EmitTest. llvm-svn: 350041
* [X86] Remove the ANDN check from EmitTest.Craig Topper2018-12-243-46/+67
| | | | | | | | Remove the TESTmr isel patterns and add another postprocessing combine for TESTrr+ANDrm->TESTmr. We already have a postprocessing combine for TESTrr+ANDrr->TESTrr. With this we can give ANDN a chance to match first. And clean it up during post processing if we ended up with just a regular AND. This is another step towards my plan to gut EmitTest and do more flag handling during isel matching or by using optimizeCompare. llvm-svn: 350038
* [DAGCombiner] limit shuffle to extend transform (PR40146)Sanjay Patel2018-12-231-4/+5
| | | | | | | | | | It's dangerous to knowingly create an illegal vector type no matter what stage of combining we're in. This prevents the missed folding/scalarization seen in: https://bugs.llvm.org/show_bug.cgi?id=40146 llvm-svn: 350034
* [DAGCombiner] allow hoisting vector bitwise logic ahead of extendsSanjay Patel2018-12-231-6/+5
| | | | llvm-svn: 350032
* [ORC] Rename register in the OrcMips64 resolver code comments. NFCSimon Atanasyan2018-12-231-2/+2
| | | | | | | The `fp` and `s8` register names are synonyms. But `fp` better reflects a purpose of the register. llvm-svn: 350023
* [ORC] clang-format OrcMips32 and OrcMips64 code. NFCSimon Atanasyan2018-12-231-24/+16
| | | | llvm-svn: 350022
* [ORC] Remove redundant instruction from MIPS resolver code. NFCSimon Atanasyan2018-12-231-8/+7
| | | | | | It's redundant to restore the `$a3` register twice. llvm-svn: 350021
* [MemCpyOpt] Use LocationSize instead of ints; NFCGeorge Burgess IV2018-12-231-3/+3
| | | | | | | | | | | | | | | Trying to keep these patches super small so they're easily post-commit verifiable, as requested in D44748. srcSize is derived from the size of an alloca, and we quit out if the size of that is > the size of the thing we're copying to. Hence, we should always copy everything over, so these sizes are precise. Don't make srcSize itself a LocationSize, since optionality isn't helpful, and we do some comparisons against other sizes elsewhere in that function. llvm-svn: 350019
* [X86] Return false from hasAndNotCompare if the comparision value is a constant.Craig Topper2018-12-231-6/+3
| | | | | | We won't end up using an ANDN instruction in this case so we should generate the same code we do for pre-BMI targets. llvm-svn: 350018
* [MemoryLocation] Use LocationSize instead of ints; NFCGeorge Burgess IV2018-12-231-20/+36
| | | | | | | | | | | | | | Trying to keep these patches super small so they're easily post-commit verifiable, as requested in D44748. This one sadly isn't *super* small, but all of the changes here are either to: - libfuncs that are passed a constant size (memcpy, memset, ...) - instructions that store/load a constant size So they have to be precise llvm-svn: 350017
* [Loads] Use LocationSize instead of ints; NFCGeorge Burgess IV2018-12-231-1/+1
| | | | | | | | | | Keeping these patches super small so they're easily post-commit verifiable, as requested in D44748. This tries to find literal loads/stores of the given type, so this has to be precise. llvm-svn: 350016
* [Lint] Use LocationSize instead of ints; NFCGeorge Burgess IV2018-12-231-2/+2
| | | | | | | Keeping these patches super small so they're easily post-commit verifiable, as requested in D44748. llvm-svn: 350015
* [AAEval] Use LocationSize instead of ints; NFCGeorge Burgess IV2018-12-231-7/+10
| | | | | | | Keeping these patches super small so they're easily post-commit verifiable, as requested in D44748. llvm-svn: 350014
* [X86] Fix an old FIXME about folding the zero constant into the OR ↵Craig Topper2018-12-232-7/+6
| | | | | | instruction we use for sequentially consistent fence in 32-bit mode without SSE2. llvm-svn: 350013
* DebugInfo: Accurately propagate the section used by a relocation when ↵David Blaikie2018-12-221-4/+4
| | | | | | | | | | | | | | | | | accessing ranges defined by low/high_pc This is difficult/not possible to test in LLVM, but is visible as a crash in LLD when parsing DWARF to generate gdb-index. This function is called by llvm-dwarfdump when parsing high_pc for non-verbose output (to print the actual high_pc rather than the low_pc relative value), but in that case llvm-dwarfdump doesn't print section names (if it did, it would hit this problem). We could add some other features to llvm-dwarfdump to expose this, but nothing really springs to my mind. I will add a test to lld, though. llvm-svn: 350010
* llvm-dwarfdump: Dump the section name/number for addr attributesDavid Blaikie2018-12-221-1/+1
| | | | llvm-svn: 350009
* [Analysis] More LocationSize cleanup; NFCGeorge Burgess IV2018-12-222-4/+4
| | | | | | | Keeping these patches super small so they're easily post-commit verifiable, as requested in D44748. llvm-svn: 350008
* [DAGCombiner] allow narrowing of add followed by truncateSanjay Patel2018-12-221-2/+1
| | | | | | | | | | | | | | | trunc (add X, C ) --> add (trunc X), C' If we're throwing away the top bits of an 'add' instruction, do it in the narrow destination type. This makes the truncate-able opcode list identical to the sibling transform done in IR (in instcombine). This change used to show regressions for x86, but those are gone after D55494. This gets us closer to deleting the x86 custom function (combineTruncatedArithmetic) that does almost the same thing. Differential Revision: https://reviews.llvm.org/D55866 llvm-svn: 350006
* [x86] add load fold patterns for movddup with vzext_loadSanjay Patel2018-12-222-0/+8
| | | | | | | | | | | The missed load folding noticed in D55898 is visible independent of that change either with an adjusted IR pattern to start or with AVX2/AVX512 (where the build vector becomes a broadcast first; movddup is not produced until we get into isel via tablegen patterns). Differential Revision: https://reviews.llvm.org/D55936 llvm-svn: 350005
* llvm-dwarfdump: Remove extraneous space between '(' and 'indexed'David Blaikie2018-12-221-2/+2
| | | | | | When dumping string or address indexes llvm-svn: 349997
* llvm-dwarfdump: Print the section name/number for addr_index attributesDavid Blaikie2018-12-221-3/+12
| | | | | | (addr attributes coming shortly) llvm-svn: 349996
* DebugInfo: Refactor named section dumping into a reusable helperDavid Blaikie2018-12-222-9/+16
| | | | | | | | | | | Currently the section name (& possibly number) is only printed on addresses in ranges - but no reason it couldn't also be displayed on other addresses (like low/high PC). Refactor in that direction by pulling out the section lookup and name ambiguity dumping logic into a reusable helper. llvm-svn: 349995
* DebugInfo: Remove extra attribute lookupDavid Blaikie2018-12-221-3/+2
| | | | llvm-svn: 349985
* [X86] FixupLEAs, reduce number of calls to getOperand and use ↵Craig Topper2018-12-221-22/+29
| | | | | | | | X86::AddrBaseReg/AddrIndexReg, etc. instead of hardcoded constants. Makes the code a little more readable. llvm-svn: 349983
* [NVPTX] Reduce stack size in NVPTXAsmPrinter::doInitialization().Justin Lebar2018-12-221-5/+2
| | | | | | | | NVPTXAsmPrinter::doInitialization() was creating an NVPTXSubtarget on the stack. This object is huge, about 80kb. Also it's slow to create. And it's all redundant; we have one in NVPTXTargetMachine anyway! llvm-svn: 349982
* libDebugInfo: Refactor error handling in range list parsingDavid Blaikie2018-12-222-15/+15
| | | | | | | | Propagate the llvm::Error a little further up. This is NFC for llvm-dwarfdump in this change, but allows ld.lld to emit more precise error messages about which object and archive the erroneous DWARF is in. llvm-svn: 349978
OpenPOWER on IntegriCloud