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| author | Petar Avramovic <Petar.Avramovic@rt-rk.com> | 2018-12-25 14:42:30 +0000 | 
|---|---|---|
| committer | Petar Avramovic <Petar.Avramovic@rt-rk.com> | 2018-12-25 14:42:30 +0000 | 
| commit | 09dff3334931052cfd0dab9dd5ae23bee6be1406 (patch) | |
| tree | b9d774be99a4aeb40dae4743889113f2545534db /llvm/lib | |
| parent | 9b25bf396041a4e9e13d5e3a2f336c7868236999 (diff) | |
| download | bcm5719-llvm-09dff3334931052cfd0dab9dd5ae23bee6be1406.tar.gz bcm5719-llvm-09dff3334931052cfd0dab9dd5ae23bee6be1406.zip | |
[MIPS GlobalISel] Select G_SELECT
Add widen scalar for type index 1 (i1 condition) for G_SELECT.
Select G_SELECT for pointer, s32(integer) and smaller low level
types on MIPS32.
Differential Revision: https://reviews.llvm.org/D56001
llvm-svn: 350063
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp | 19 | ||||
| -rw-r--r-- | llvm/lib/Target/Mips/MipsInstructionSelector.cpp | 9 | ||||
| -rw-r--r-- | llvm/lib/Target/Mips/MipsLegalizerInfo.cpp | 5 | ||||
| -rw-r--r-- | llvm/lib/Target/Mips/MipsRegisterBankInfo.cpp | 7 | 
4 files changed, 32 insertions, 8 deletions
| diff --git a/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp b/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp index 274bc4bf695..facbafaf509 100644 --- a/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp +++ b/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp @@ -777,15 +777,18 @@ LegalizerHelper::widenScalar(MachineInstr &MI, unsigned TypeIdx, LLT WideTy) {      return Legalized;    case TargetOpcode::G_SELECT: -    if (TypeIdx != 0) -      return UnableToLegalize; -    // Perform operation at larger width (any extension is fine here, high bits -    // don't affect the result) and then truncate the result back to the -    // original type.      Observer.changingInstr(MI); -    widenScalarSrc(MI, WideTy, 2, TargetOpcode::G_ANYEXT); -    widenScalarSrc(MI, WideTy, 3, TargetOpcode::G_ANYEXT); -    widenScalarDst(MI, WideTy); +    if (TypeIdx == 0) { +      // Perform operation at larger width (any extension is fine here, high +      // bits don't affect the result) and then truncate the result back to the +      // original type. +      widenScalarSrc(MI, WideTy, 2, TargetOpcode::G_ANYEXT); +      widenScalarSrc(MI, WideTy, 3, TargetOpcode::G_ANYEXT); +      widenScalarDst(MI, WideTy); +    } else { +      // Explicit extension is required here since high bits affect the result. +      widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_ZEXT); +    }      Observer.changedInstr(MI);      return Legalized; diff --git a/llvm/lib/Target/Mips/MipsInstructionSelector.cpp b/llvm/lib/Target/Mips/MipsInstructionSelector.cpp index 4964ca9cbe1..b041590ee34 100644 --- a/llvm/lib/Target/Mips/MipsInstructionSelector.cpp +++ b/llvm/lib/Target/Mips/MipsInstructionSelector.cpp @@ -172,6 +172,15 @@ bool MipsInstructionSelector::select(MachineInstr &I,      I.eraseFromParent();      return true;    } +  case G_SELECT: { +    // Handle operands with pointer type. +    MI = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::MOVN_I_I)) +             .add(I.getOperand(0)) +             .add(I.getOperand(2)) +             .add(I.getOperand(1)) +             .add(I.getOperand(3)); +    break; +  }    case G_CONSTANT: {      int Imm = I.getOperand(1).getCImm()->getValue().getLimitedValue();      unsigned LUiReg = MRI.createVirtualRegister(&Mips::GPR32RegClass); diff --git a/llvm/lib/Target/Mips/MipsLegalizerInfo.cpp b/llvm/lib/Target/Mips/MipsLegalizerInfo.cpp index 0d80bd479d5..c629f02af00 100644 --- a/llvm/lib/Target/Mips/MipsLegalizerInfo.cpp +++ b/llvm/lib/Target/Mips/MipsLegalizerInfo.cpp @@ -35,6 +35,11 @@ MipsLegalizerInfo::MipsLegalizerInfo(const MipsSubtarget &ST) {    getActionDefinitionsBuilder({G_LOAD, G_STORE})        .legalForCartesianProduct({p0, s32}, {p0}); +  getActionDefinitionsBuilder(G_SELECT) +      .legalForCartesianProduct({p0, s32}, {s32}) +      .minScalar(0, s32) +      .minScalar(1, s32); +    getActionDefinitionsBuilder({G_AND, G_OR, G_XOR})        .legalFor({s32})        .clampScalar(0, s32, s32); diff --git a/llvm/lib/Target/Mips/MipsRegisterBankInfo.cpp b/llvm/lib/Target/Mips/MipsRegisterBankInfo.cpp index 53b9e42dc63..6af1f10189d 100644 --- a/llvm/lib/Target/Mips/MipsRegisterBankInfo.cpp +++ b/llvm/lib/Target/Mips/MipsRegisterBankInfo.cpp @@ -111,6 +111,13 @@ MipsRegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {                              &Mips::ValueMappings[Mips::GPRIdx],                              &Mips::ValueMappings[Mips::GPRIdx]});      break; +  case G_SELECT: +    OperandsMapping = +        getOperandsMapping({&Mips::ValueMappings[Mips::GPRIdx], +                            &Mips::ValueMappings[Mips::GPRIdx], +                            &Mips::ValueMappings[Mips::GPRIdx], +                            &Mips::ValueMappings[Mips::GPRIdx]}); +    break;    default:      return getInvalidInstructionMapping();    } | 

