summaryrefslogtreecommitdiffstats
path: root/llvm/lib
Commit message (Collapse)AuthorAgeFilesLines
* [AMDGPU] Throw away more dead code. NFCI.Davide Italiano2017-07-141-16/+0
| | | | llvm-svn: 308055
* [Dominators] Implement incremental insertionsJakub Kuderski2017-07-141-0/+5
| | | | | | | | | | | | | | | | | Summary: This patch introduces incremental edge insertions based on the Depth Based Search algorithm. Insertions should work for both dominators and postdominators. Reviewers: dberlin, grosser, davide, sanjoy, brzycki Reviewed By: dberlin Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D35341 llvm-svn: 308054
* Fix mixed line terminators. NFC.Dimitry Andric2017-07-141-3/+3
| | | | llvm-svn: 308052
* [EarlyCSE] Handle calls with no MemorySSA info.Geoff Berry2017-07-141-1/+15
| | | | | | | | | | | | | | | | | | Summary: When checking for memory dependencies between calls using MemorySSA, handle cases where the calls have no MemoryAccess associated with them because the AA analysis being used has determined that the call does not read/write memory. Fixes PR33756 Reviewers: dberlin, davide Subscribers: mcrosier, llvm-commits, Prazek Differential Revision: https://reviews.llvm.org/D35317 llvm-svn: 308051
* [JumpThreading] Add a pattern to TryToUnfoldSelectInCurrBB()Haicheng Wu2017-07-141-32/+50
| | | | | | | | | | | | | | | | Add the following pattern to TryToUnfoldSelectInCurrBB() bb: %p = phi [0, %bb1], [1, %bb2], [0, %bb3], [1, %bb4], ... %c = cmp %p, 0 %s = select %c, trueval, falseval The Select in the above pattern will be unfolded and then jump-threaded. The current implementation does not allow CMP in the middle of PHI and Select. Differential Revision: https://reviews.llvm.org/D34762 llvm-svn: 308050
* [Hexagon] Replace ISD opcode VPACK with VPACKE/VPACKO, NFCKrzysztof Parzyszek2017-07-143-51/+45
| | | | | | This breaks up pack-even and pack-odd into two separate operations. llvm-svn: 308049
* [AMDGPU] Garbage collect dead code. NFCI.Davide Italiano2017-07-141-16/+0
| | | | | | Unbreaks the build with GCC7. llvm-svn: 308047
* [Dominators] Make IsPostDominator a template parameterJakub Kuderski2017-07-149-17/+33
| | | | | | | | | | | | | | | | | Summary: DominatorTreeBase used to have IsPostDominators (bool) member to indicate if the tree is a dominator or a postdominator tree. This made it possible to switch between the two 'modes' at runtime, but it isn't used in practice anywhere. This patch makes IsPostDominator a template argument. This way, it is easier to switch between different algorithms at compile-time based on this argument and design external utilities around it. It also makes it impossible to incidentally assign a postdominator tree to a dominator tree (and vice versa), and to further simplify template code in GenericDominatorTreeConstruction. Reviewers: dberlin, sanjoy, davide, grosser Reviewed By: dberlin Subscribers: mzolotukhin, llvm-commits Differential Revision: https://reviews.llvm.org/D35315 llvm-svn: 308040
* [AMDGPU] Do not insert an instruction into worklist twice in movetovaluAlfred Huang2017-07-142-20/+23
| | | | | | | | | | In moveToVALU(), move to vector ALU is performed, all instrs in the use chain will be visited. We do not want the same node to be pushed to the visit worklist more than once. Differential Revision: https://reviews.llvm.org/D34726 llvm-svn: 308039
* [Hexagon] Add intrinsics for data cache operationsKrzysztof Parzyszek2017-07-142-0/+16
| | | | | | | | | | | | | This is the LLVM part, adding definitions for void @llvm.hexagon.Y2.dccleana(i8*) void @llvm.hexagon.Y2.dccleaninva(i8*) void @llvm.hexagon.Y2.dcinva(i8*) void @llvm.hexagon.Y2.dczeroa(i8*) void @llvm.hexagon.Y4.l2fetch(i8*, i32) void @llvm.hexagon.Y5.l2fetch(i8*, i64) The clang part will follow. llvm-svn: 308032
* [InstCombine] convert bitwise (in)equality checks to logical ops (PR32401)Sanjay Patel2017-07-141-3/+15
| | | | | | | | | | | | | As discussed in: https://bugs.llvm.org/show_bug.cgi?id=32401 we have a backend transform to undo this: https://reviews.llvm.org/rL299542 when it's likely that the xor version leads to better codegen, but we want this form in IR for better analysis and simplification potential. llvm-svn: 308031
* Revert "Reland "[mips][mt][6/7] Add support for mftr, mttr instructions.""Simon Dardis2017-07-146-372/+0
| | | | | | | | | FileCheck is crashing on in the input file, so reverting again while I investigate. This reverts r308023. llvm-svn: 308030
* [SystemZ] Minor fixing in SystemZScheduleZ196.tdJonas Paulsson2017-07-141-71/+92
| | | | | | | Some minor corrections for the recently added instructions. Review: Ulrich Weigand llvm-svn: 308028
* Improve Aliasing of operations to static allocaNirav Dave2017-07-141-6/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Recommiting after adding check to avoid miscomputing alias information on addresses of the same base but different subindices. Memory accesses offset from frame indices may alias, e.g., we may merge write from function arguments passed on the stack when they are contiguous. As a result, when checking aliasing, we consider the underlying frame index's offset from the stack pointer. Static allocs are realized as stack objects in SelectionDAG, but its offset is not set until post-DAG causing DAGCombiner's alias check to consider access to static allocas to frequently alias. Modify isAlias to consider access between static allocas and access from other frame objects to be considered aliasing. Many test changes are included here. Most are fixes for tests which indirectly relied on our aliasing ability and needed to be modified to preserve their original intent. The remaining tests have minor improvements due to relaxed ordering. The exception is CodeGen/X86/2011-10-19-widen_vselect.ll which has a minor degradation dispite though the pre-legalized DAG is improved. Reviewers: rnk, mkuper, jonpa, hfinkel, uweigand Reviewed By: rnk Subscribers: sdardis, nemanjai, javed.absar, llvm-commits Differential Revision: https://reviews.llvm.org/D33345 llvm-svn: 308025
* [SystemZ] Enable LoopDataPrefetch pass.Jonas Paulsson2017-07-142-1/+7
| | | | | | | | Loop data prefetching has shown some improvements on benchmarks, and is enabled at -O1 and above. Review: Ulrich Weigand llvm-svn: 308024
* Reland "[mips][mt][6/7] Add support for mftr, mttr instructions.""Simon Dardis2017-07-146-0/+372
| | | | | | | | | | | | | | | | | | | | | | | | Unlike many other instructions, these instructions have aliases which take coprocessor registers, gpr register, accumulator (and dsp accumulator) registers, floating point registers, floating point control registers and coprocessor 2 data and control operands. For the moment, these aliases are treated as pseudo instructions which are expanded into the underlying instruction. As a result, disassembling these instructions shows the underlying instruction and not the alias. Reviewers: slthakur, atanasyan Differential Revision: https://reviews.llvm.org/D35253 The last version of this patch broke one of the expensive checks buildbots, this version changes the failing test/MC/Mips/mt/invalid.s and other invalid tests to write the errors to a file and run FileCheck on that, rather than relying on the 'not llvm-mc ... <%s 2>&1 | Filecheck %s' idiom. Hopefully this will sarisfy the buildbot. llvm-svn: 308023
* Reverting commit 308011.Zoran Jovanovic2017-07-141-101/+14
| | | | llvm-svn: 308017
* [mips][microMIPS] Extending size reduction pass with ADDIUSP and ADDIUR1SPZoran Jovanovic2017-07-141-14/+101
| | | | | | | | | | | | | | Author: milena.vujosevic.janicic Reviewers: sdardis The patch extends size reduction pass for MicroMIPS. The following instructions are examined and transformed, if possible: ADDIU instruction is transformed into 16-bit instruction ADDIUSP ADDIU instruction is transformed into 16-bit instruction ADDIUR1SP Function InRange is changed to avoid left shifting of negative values, since that caused some sanitizer tests to fail (so the previous patch Differential Revision: https://reviews.llvm.org/D34511 llvm-svn: 308011
* [ARM] GlobalISel: Support G_BRCONDDiana Picus2017-07-143-0/+29
| | | | | | | | | | | | Insert a TSTri to set the flags and a Bcc to branch based on their values. This is a bit inefficient in the (common) cases where the condition for the branch comes from a compare right before the branch, since we set the flags both as part of the compare lowering and as part of the branch lowering. We're going to live with that until we settle on a principled way to handle this kind of situation, which occurs with other patterns as well (combines might be the way forward here). llvm-svn: 308009
* [SystemZ] Minor fixing in SystemZScheduleZEC12.tdJonas Paulsson2017-07-141-70/+91
| | | | | | | Some minor corrections for the recently added instructions. Review: Ulrich Weigand llvm-svn: 308007
* [ARM] Allow rematerialization of ARM Thumb literal pool loadsSam Parker2017-07-141-3/+17
| | | | | | | | | | | | | | | | | | Constants are crucial for code size in the ARM Thumb-1 instruction set. The 16 bit instruction size often does not offer enough space for immediate arguments. This means that additional instructions are frequently used to load constants into registers. Since constants are hoisted, this can lead to significant register spillage if they are used multiple times in a single function. This can be avoided by rematerialization, i.e. recomputing a constant instead of reloading it from the stack. This patch fixes the rematerialization of literal pool loads in the ARM Thumb instruction set. Patch by Philip Ginsbach Differential Revision: https://reviews.llvm.org/D33936 llvm-svn: 308004
* [IRCE] Fix corner case with Start = INT_MAXMax Kazantsev2017-07-141-5/+9
| | | | | | | | | | | | | | | | | | | | When iterating through loop for (int i = INT_MAX; i > 0; i--) We fail to generate the pre-loop for it. It happens because we use the overflown value in a comparison predicate when identifying whether or not we need it. In old logic, we used SLE predicate against Greatest value which exceeds all seen values of the IV and might be overflown. Now we use the GreatestSeen value of this IV with SLT predicate. Also added a test that ensures that a pre-loop is generated for such loops. Differential Revision: https://reviews.llvm.org/D35347 llvm-svn: 308001
* Add a set of comments explaining why getSubtargetImpl() is deleted on these ↵Eric Christopher2017-07-144-0/+8
| | | | | | targets. llvm-svn: 307999
* [SLPVectorizer] Add an extra parameter to alreadyVectorized function, NFCI.Dinar Temirbulatov2017-07-141-8/+8
| | | | llvm-svn: 307996
* Remove set but not used variables from the debug info verifier code.Eric Christopher2017-07-141-6/+1
| | | | llvm-svn: 307987
* [libFuzzer] update the comments in afl/afl_driver.cppKostya Serebryany2017-07-141-2/+2
| | | | llvm-svn: 307981
* [libFuzzer] remove stale code; NFCKostya Serebryany2017-07-143-52/+0
| | | | llvm-svn: 307980
* AMDGPU: Detect kernarg segment pointerMatt Arsenault2017-07-142-2/+9
| | | | | | | | This is necessary to pass the kernarg segment pointer to callee functions. Also don't unconditionally enable for kernels. llvm-svn: 307978
* [libFuzzer] simplify the handling of memmem/strstrKostya Serebryany2017-07-1410-129/+61
| | | | llvm-svn: 307977
* [AMDGPU] fcaninicalize optimization for GFX9+Stanislav Mekhanoshin2017-07-132-8/+23
| | | | | | | | | | | | | | Since GFX9 supports denorm modes for v_min_f32/v_max_f32 that is possible to further optimize fcanonicalize and remove it if applied to min/max given their operands are known not to be an sNaN or that sNaNs are not supported. Additionally we can remove fcanonicalize if denorms are supported for the VT and we know that its argument is never a NaN. Differential Revision: https://reviews.llvm.org/D35335 llvm-svn: 307976
* [DWARF] Introduce verification for the unit header chain in .debug_info ↵Spyridoula Gravani2017-07-132-0/+94
| | | | | | | | | | | | | | | section to llvm-dwarfdump. This patch adds verification checks for the unit header chain in the .debug_info section. Specifically, for each unit in the .debug_info section, the verifier checks that: The unit length is valid (i.e. the unit can actually fit in the .debug_info section) The dwarf version of the unit is valid The address size is valid (4 or 8) The unit type (if the unit is in dwarf5) is valid The debug_abbrev_offset is valid llvm-svn: 307975
* [libFuzzer] move code around; NFCKostya Serebryany2017-07-132-69/+60
| | | | llvm-svn: 307973
* AMDGPU: Annotate call graph with used featuresMatt Arsenault2017-07-132-68/+144
| | | | | | | Previously this wouldn't detect used features indirectly used in callee functions. llvm-svn: 307967
* [Dominators] Simplify templatesJakub Kuderski2017-07-131-16/+6
| | | | | | | | | | | | | | Summary: DominatorTreeBase and related classes used overcomplicated template machinery. This patch simplifies them and gets rid of DominatorTreeBaseTraits and DominatorTreeBaseByTraits, which weren't actually used outside the DomTree construction. Reviewers: dberlin, sanjoy, davide, grosser Reviewed By: dberlin, davide, grosser Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D35285 llvm-svn: 307953
* [NFC] Move DEBUG_TYPE below includes in HexagonJakub Kuderski2017-07-137-14/+14
| | | | llvm-svn: 307947
* [PDB] Fix type server handling for archivesReid Kleckner2017-07-133-16/+13
| | | | | | | | | | | | | | | | | | | Summary: This fixes type indices for SDK or CRT static archives. Previously we'd try to look next to the archive object file path, which would not exist on the local machine. Also error out if we can't resolve a type server record. Hypothetically we can recover from this error by discarding debug info for this object, but that is not yet implemented. Reviewers: ruiu, amccarth Subscribers: aprantl, hiraditya, llvm-commits Differential Revision: https://reviews.llvm.org/D35369 llvm-svn: 307946
* [NFC] Move DEBUG_TYPE macro below includes...Jakub Kuderski2017-07-131-2/+2
| | | | | | in MachineCombiner.cpp. llvm-svn: 307940
* Revert "[mips][mt][6/7] Add support for mftr, mttr instructions."Simon Dardis2017-07-136-372/+0
| | | | | | | This reverts r307836, it broke one of the buildbots. Reverting while I investigate. llvm-svn: 307939
* [Hexagon] Use VSPLAT instead of COMBINE for vectors of type v2i32, NFCKrzysztof Parzyszek2017-07-132-29/+28
| | | | | | This cleans up the vector shift patterns. llvm-svn: 307935
* [PowerPC] Ensure displacements for DQ-Form instructions are multiples of 16Nemanja Ivanovic2017-07-137-67/+126
| | | | | | | | | | | | | As outlined in the PR, we didn't ensure that displacements for DQ-Form instructions are multiples of 16. Since the instruction encoding encodes a quad-word displacement, a sub-16 byte displacement is meaningless and ends up being encoded incorrectly. Fixes https://bugs.llvm.org/show_bug.cgi?id=33671. Differential Revision: https://reviews.llvm.org/D35007 llvm-svn: 307934
* Fix unused variable warning on EXPENSIVE_CHECKS release builds. NFCI.Simon Pilgrim2017-07-131-1/+1
| | | | llvm-svn: 307929
* [AArch64] Implement support for windows style vararg functionsMartin Storsjo2017-07-135-8/+57
| | | | | | | | | | | Pass parameters properly in calls to such functions (pass all floats in integer registers), and handle va_start properly (allocate stack immediately below the arguments on the stack, to save the register arguments into a single continuous array). Differential Revision: https://reviews.llvm.org/D35006 llvm-svn: 307928
* Put std::mutex usage behind #ifdefs to pacify the sanitizer buildbotReid Kleckner2017-07-131-0/+22
| | | | llvm-svn: 307925
* Support: Add llvm::center_justify.Frederich Munch2017-07-131-6/+23
| | | | | | | | | | | | | | Summary: Completes the set. Reviewers: ruiu Reviewed By: ruiu Subscribers: ruiu, llvm-commits Differential Revision: https://reviews.llvm.org/D35278 llvm-svn: 307922
* Reapply [GlobalOpt] Remove unreachable blocks before optimizing a function.Davide Italiano2017-07-131-0/+18
| | | | | | | This commit reapplies r307215 now that we found out and fixed the cause of the cfi test failure (in r307871). llvm-svn: 307920
* [AArch64] Enable the mnemonic spell checkerSjoerd Meijer2017-07-131-7/+14
| | | | | | | | | The AsmParser mnemonic spell checker was introduced in r307148 and enabled only for ARM. This patch enables it for AArch64. Differential Revision: https://reviews.llvm.org/D35357 llvm-svn: 307918
* [AArch64] Add an SVE target feature to the backend and TargetParser.Amara Emerson2017-07-134-0/+9
| | | | | | | The feature will be used properly once assembler/disassembler support begins to land. llvm-svn: 307917
* [AArch64] Add preliminary support for ARMv8.1 SUB/AND atomicsMatthew Simpson2017-07-133-3/+14
| | | | | | | This patch is a follow-up to r305893 and adds preliminary support for the fetch_sub and fetch_and operations. llvm-svn: 307913
* [RuntimeUnrolling] Update DomTree correctly when exit blocks have successorsAnna Thomas2017-07-131-2/+28
| | | | | | | | | | | | | | | | Summary: When we runtime unroll with multiple exit blocks, we also need to update the immediate dominators of the immediate successors of the exit blocks. Reviewers: reames, mkuper, mzolotukhin, apilipenko Reviewed by: mzolotukhin Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D35304 llvm-svn: 307909
* Reland "[mips] Fix multiprecision arithmetic."Simon Dardis2017-07-135-230/+201
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | For multiprecision arithmetic on MIPS, rather than using ISD::ADDE / ISD::ADDC, get SelectionDAG to break down the operation into ISD::ADDs and ISD::SETCCs. For MIPS, only the DSP ASE has a carry flag, so in the general case it is not useful to directly support ISD::{ADDE, ADDC, SUBE, SUBC} nodes. Also improve the generation code in such cases for targets with TargetLoweringBase::ZeroOrOneBooleanContent by directly using the result of the comparison node rather than using it in selects. Similarly for ISD::SUBE / ISD::SUBC. Address optimization breakage by moving the generation of MIPS specific integer multiply-accumulate nodes to before legalization. This revolves PR32713 and PR33424. Thanks to Simonas Kazlauskas and Pirama Arumuga Nainar for reporting the issue! Reviewers: slthakur Differential Revision: https://reviews.llvm.org/D33494 The previous version of this patch was too aggressive in producing fused integer multiple-addition instructions. llvm-svn: 307906
OpenPOWER on IntegriCloud