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authorMatt Arsenault <Matthew.Arsenault@amd.com>2017-07-14 00:11:13 +0000
committerMatt Arsenault <Matthew.Arsenault@amd.com>2017-07-14 00:11:13 +0000
commit23e4df6a598e6e0d19b064080ef38961c9af6e95 (patch)
tree3dc605696a508d18f65ac011b06c1e082ffac4b5 /llvm/lib
parentf64b8487f98125ec9c878656ef12081b67f04bb0 (diff)
downloadbcm5719-llvm-23e4df6a598e6e0d19b064080ef38961c9af6e95.tar.gz
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AMDGPU: Detect kernarg segment pointer
This is necessary to pass the kernarg segment pointer to callee functions. Also don't unconditionally enable for kernels. llvm-svn: 307978
Diffstat (limited to 'llvm/lib')
-rw-r--r--llvm/lib/Target/AMDGPU/AMDGPUAnnotateKernelFeatures.cpp6
-rw-r--r--llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp5
2 files changed, 9 insertions, 2 deletions
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUAnnotateKernelFeatures.cpp b/llvm/lib/Target/AMDGPU/AMDGPUAnnotateKernelFeatures.cpp
index c837180334c..d1580ff4e19 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUAnnotateKernelFeatures.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUAnnotateKernelFeatures.cpp
@@ -150,6 +150,9 @@ static StringRef intrinsicToAttrName(Intrinsic::ID ID, bool &IsQueuePtr) {
return "amdgpu-dispatch-ptr";
case Intrinsic::amdgcn_dispatch_id:
return "amdgpu-dispatch-id";
+ case Intrinsic::amdgcn_kernarg_segment_ptr:
+ case Intrinsic::amdgcn_implicitarg_ptr:
+ return "amdgpu-kernarg-segment-ptr";
case Intrinsic::amdgcn_queue_ptr:
case Intrinsic::trap:
case Intrinsic::debugtrap:
@@ -181,7 +184,8 @@ static void copyFeaturesToFunction(Function &Parent, const Function &Callee,
{ "amdgpu-work-group-id-y" },
{ "amdgpu-work-group-id-z" },
{ "amdgpu-dispatch-ptr" },
- { "amdgpu-dispatch-id" }
+ { "amdgpu-dispatch-id" },
+ { "amdgpu-kernarg-segment-ptr" }
};
if (handleAttr(Parent, Callee, "amdgpu-queue-ptr"))
diff --git a/llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp b/llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp
index 3203c38dae3..7fe671a533a 100644
--- a/llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp
@@ -92,7 +92,7 @@ SIMachineFunctionInfo::SIMachineFunctionInfo(const MachineFunction &MF)
CallingConv::ID CC = F->getCallingConv();
if (CC == CallingConv::AMDGPU_KERNEL || CC == CallingConv::SPIR_KERNEL) {
- KernargSegmentPtr = true;
+ KernargSegmentPtr = !F->arg_empty();
WorkGroupIDX = true;
WorkItemIDX = true;
} else if (CC == CallingConv::AMDGPU_PS) {
@@ -154,6 +154,9 @@ SIMachineFunctionInfo::SIMachineFunctionInfo(const MachineFunction &MF)
ImplicitBufferPtr = true;
}
+ if (F->hasFnAttribute("amdgpu-kernarg-segment-ptr"))
+ KernargSegmentPtr = true;
+
// We don't need to worry about accessing spills with flat instructions.
// TODO: On VI where we must use flat for global, we should be able to omit
// this if it is never used for generic access.
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