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* [AMDGPU] Refactor VOPC instruction TD definitionsValery Pykhtin2016-09-196-648/+1118
| | | | | | Differential Revision: https://reviews.llvm.org/D24546 llvm-svn: 281903
* [AArch64] Fix encoding for lsl #12 in add/sub immediatesDiana Picus2016-09-191-2/+2
| | | | | | | | | | | Whenever an add/sub immediate needs a fixup, we set that immediate field to zero, which is correct, but we also set the shift bits to zero, which is not true for instructions that use lsl #12. This patch makes sure that if lsl #12 was used, it will appear in the encoding of the instruction. Differential Revision: https://reviews.llvm.org/D23930 llvm-svn: 281898
* [AMDGPU] Fix s_branch with -1 offsetSam Kolton2016-09-191-5/+2
| | | | | | | | | | | | | | | | | | | Summary: In case s_branch instruction target is itself backend should emit offset -1 but instead it emit 0. ''' label: s_branch label // should emit [0xff,0xff,0x82,0xbf] ''' Tom, Matt: why are we adjusting fixup values in applyFixup() method instead of processFixup()? processFixup() is calling adjustFixupValue() but does nothing with its result. Reviewers: vpykhtin, artem.tamazov, tstellarAMD Subscribers: arsenm, kzhuravl, wdng, nhaehnle, yaxunl Differential Revision: https://reviews.llvm.org/D24671 llvm-svn: 281896
* Add @llvm.dbg.value entries for the phi node created by -mem2regKeith Walker2016-09-192-0/+47
| | | | | | | | | | | | | | | | | | | | | | | When phi nodes are created in the -mem2reg phase, the @llvm.dbg.declare entries are converted to @llvm.dbg.value entries at the place where the store instructions existed. However no entry is created to describe the resulting value of the phi node. The effect of this is especially noticeable in for loops which have a constant for the intial value; the loop control variable's location would be described as the intial constant value in the loop body once the -mem2reg optimization phase was run. This change adds the creation of the @llvm.dbg.value entries to describe variables whose location is the result of a phi node created in -mem2reg. Also when the phi node is finally lowered to a machine instruction it is important that the lowered "load" instruction is placed before the associated DEBUG_VALUE entry describing the value loaded. Differential Revision: https://reviews.llvm.org/D23715 llvm-svn: 281895
* [Thumb] Set correct initial mapping symbol for big-endian thumbOliver Stannard2016-09-191-1/+2
| | | | | | | | | | The initial mapping symbol state is set from the triple, but we only checked for the little-endian thumb triple, so could end up with an ARM mapping symbol for big-endian thumb. Differential Revision: https://reviews.llvm.org/D24553 llvm-svn: 281894
* ARM: check alignment before transforming ldr -> ldm (or similar).Tim Northover2016-09-192-8/+28
| | | | | | | | | ldm and stm instructions always require 4-byte alignment on the pointer, but we weren't checking this before trying to reduce code-size by replacing a post-indexed load/store with them. Unfortunately, we were also dropping this incormation in DAG ISel too, but that's easy enough to fix. llvm-svn: 281893
* [SimplifyCFG] Update (AND) IR flags when CSE'ing instructionsJames Molloy2016-09-191-2/+4
| | | | | | | | We were updating metadata but not IR flags. Because we pick an arbitrary instruction to be the CSE candidate, it comes down to luck (50% or less chance) if this results in broken codegen or not, which is why PR30373 which is actually not the fault of the commit it was bisected down to. Fixes PR30373. llvm-svn: 281889
* [X86,AVX-512] Use INSERT_SUBREG instead of SUBREG_TO_REG when the input is ↵Craig Topper2016-09-192-32/+44
| | | | | | | | not the output of an instruction. SUBREG_TO_REG is supposed to indicate that the super register has been zeroed, but we can't prove that if we don't know where it came from. llvm-svn: 281885
* [AVX-512] Add support for lowering fp_to_f16 and f16_to_fp when VLX is ↵Craig Topper2016-09-193-2/+23
| | | | | | | | supported regardless of whether F16C is also supported. Still need to add support for lowering using AVX512F when neither VLX or F16C is supported. llvm-svn: 281884
* [XRay] ARM 32-bit no-Thumb support in LLVMDean Michael Berris2016-09-1911-62/+224
| | | | | | | | | | | | This is a port of XRay to ARM 32-bit, without Thumb support yet. The XRay instrumentation support is moving up to AsmPrinter. This is one of 3 commits to different repositories of XRay ARM port. The other 2 are: https://reviews.llvm.org/D23932 (Clang test) https://reviews.llvm.org/D23933 (compiler-rt) Differential Revision: https://reviews.llvm.org/D23931 llvm-svn: 281878
* Handle Invoke during sample profiler annotation: make it inlinable.Dehao Chen2016-09-181-23/+32
| | | | | | | | | | | | Summary: Previously we reline on inst-combine to remove inlinable invoke instructions. This causes trouble because a few extra optimizations are schedule early that could introduce too much CFG change (e.g. simplifycfg removes too much control flow). This patch handles invoke instruction in-place during sample profile annotation, so that we do not rely on instcombine to remove those invoke instructions. Reviewers: davidxl, dnovillo Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D24409 llvm-svn: 281870
* [AVX-512] Don't lower CVTPD2PS intrinsics to ISD::FP_ROUND with an X86 ↵Craig Topper2016-09-183-4/+30
| | | | | | | | rounding mode encoding in the second operand. This immediate should only be 0 or 1 and indicates if the truncation loses precision. Also enhance an assert in SelectionDAG::getNode to flag this sort of problem in the future. llvm-svn: 281868
* [AVX-512] Stop lowering avx512_mask_sqrt intrinsics to ISD:FSQRT with a ↵Craig Topper2016-09-181-2/+2
| | | | | | second operand containing an X86 specific rounding mode encoding that doesn't belong. llvm-svn: 281867
* [libFuzzer] add -print_coverage=1 flag to print coverage directly from ↵Kostya Serebryany2016-09-188-10/+45
| | | | | | libFuzzer llvm-svn: 281866
* Fix covered-switch-default warningSimon Pilgrim2016-09-181-5/+4
| | | | llvm-svn: 281865
* [X86] Fix typo in comment. NFCCraig Topper2016-09-181-1/+1
| | | | llvm-svn: 281862
* [AVX-512] Add memory load patterns for the legacy SSE scalar fp to integer ↵Craig Topper2016-09-181-1/+16
| | | | | | conversion intrinsics to be consistent across all intruction sets. llvm-svn: 281861
* [AVX-512] Remove COPY_TO_REGCLASS from a few patterns that already had the ↵Craig Topper2016-09-181-8/+8
| | | | | | correct register class. llvm-svn: 281860
* Fix built bot failureXinliang David Li2016-09-181-1/+1
| | | | llvm-svn: 281859
* [Profile] Implement select instruction instrumentation in IR PGOXinliang David Li2016-09-182-11/+151
| | | | | | Differential Revision: http://reviews.llvm.org/D23727 llvm-svn: 281858
* [Loop Vectorizer] Consecutive memory access - fixed and simplifiedElena Demikhovsky2016-09-182-85/+9
| | | | | | | | | Amended consecutive memory access detection in Loop Vectorizer. Load/Store were not handled properly without preceding GEP instruction. Differential Revision: https://reviews.llvm.org/D20789 llvm-svn: 281853
* [X86][SSE] Improve recognition of uitofp conversions that can be performed ↵Simon Pilgrim2016-09-182-7/+9
| | | | | | | | | | | | | | as sitofp With D24253 we can now use SelectionDAG::SignBitIsZero with vector operations. This patch uses SelectionDAG::SignBitIsZero to recognise that a zero sign bit means that we can use a sitofp instead of a uitofp (which is not directly support on pre-AVX512 hardware). While AVX512 does provide support for uitofp, the conversion to sitofp should not cause any regressions. Differential Revision: https://reviews.llvm.org/D24343 llvm-svn: 281852
* [Loop vectorizer] Simplified GEP cloning. NFC.Elena Demikhovsky2016-09-181-35/+26
| | | | | | | | | Simplified GEP cloning in vectorizeMemoryInstruction(). Added an assertion that checks consecutive GEP, which should have only one loop-variant operand. Differential Revision: https://reviews.llvm.org/D24557 llvm-svn: 281851
* Change the order of the splitted store from high - low to low - high.Wei Mi2016-09-181-2/+2
| | | | | | | It is a trivial change which could make the testcase easier to be reused for the store splitting in CodeGenPrepare. llvm-svn: 281846
* [libFuzzer] use 'if guard' instead of 'if guard >= 0' with trace-pc; change ↵Kostya Serebryany2016-09-183-47/+47
| | | | | | the guard type to intptr_t; use separate array for 8-bit counters llvm-svn: 281845
* [lib/LTO] Try harder to reduce code duplication. NFCI.Davide Italiano2016-09-171-13/+14
| | | | llvm-svn: 281843
* [ThinLTO] Ensure anonymous globals renamed even at -O0Teresa Johnson2016-09-171-1/+9
| | | | | | | | | | | | | | | | | | | | | | Summary: This fixes an issue when files are compiled with -flto=thin at default -O0. We need to rename anonymous globals before attempting to write the module summary because all values need names for the summary. This was happening at -O1 and above, but not before the early exit when constructing the pipeline for -O0. Also add an internal -prepare-for-thinlto option to enable this to be tested via opt. Fixes PR30419. Reviewers: mehdi_amini Subscribers: probinson, llvm-commits, mehdi_amini Differential Revision: https://reviews.llvm.org/D24701 llvm-svn: 281840
* [X86][SSE] Improve target shuffle mask extractionSimon Pilgrim2016-09-171-10/+14
| | | | | | Add ability to extract vXi64 'vzext_movl' masks on 32-bit targets llvm-svn: 281834
* [Hexagon] segv while processing SUnit with nullNodePtrRon Lieberman2016-09-171-0/+4
| | | | | | Added BoundaryNode check to isBestZeroLatency function. llvm-svn: 281825
* AMDGPU: Fix broken FrameIndex handlingMatt Arsenault2016-09-175-99/+19
| | | | | | | | | | | | | | | | | We were trying to avoid using a FrameIndex operand in non-pointer operands in a convoluted way, and would break because of using TargetFrameIndex. The TargetFrameIndex should only be used in the case where it makes sense to fold it as part of the addressing mode, otherwise it requires materialization like a normal constant. This wasn't working reliably and failed in the added testcase, hitting the assert when processing the frame index. The TargetFrameIndex was coming from trying to produce an AssertZext limiting the maximum stack size. I'm not sure this was correct to begin with, because it is apparently possible to have a single workitem dispatch that requires all 4G of private memory. llvm-svn: 281824
* AMDGPU: Rename spill operands to match real instructionMatt Arsenault2016-09-172-13/+13
| | | | llvm-svn: 281823
* AMDGPU: Push bitcasts through build_vectorMatt Arsenault2016-09-171-0/+27
| | | | | | | | This reduces the number of copies and reg_sequences when using fp constant vectors. This significantly reduces the code size in local-stack-alloc-bug.ll llvm-svn: 281822
* [libFuzzer] properly reset the guards when reseting the coverage. Also try ↵Kostya Serebryany2016-09-173-1/+12
| | | | | | to fix check-fuzzer on the bot llvm-svn: 281814
* Don't create a SymbolTable in Function when the LLVMContext discards value ↵Mehdi Amini2016-09-178-15/+19
| | | | | | | | | | | | | | names (NFC) The ValueSymbolTable is used to detect name conflict and rename instructions automatically. This is not needed when the value names are automatically discarded by the LLVMContext. No functional change intended, just saving a little bit of memory. This is a recommit of r281806 after fixing the accessor to return a pointer instead of a reference and updating all the call-sites. llvm-svn: 281813
* [MIR Parser] Fix Build!Mehdi Amini2016-09-171-1/+1
| | | | | | Last-second refactoring before push was bad idea... llvm-svn: 281812
* MIR Parser: issue an error when the Context discard value names.Mehdi Amini2016-09-171-0/+8
| | | | | | This is in line with the LLParser behavior llvm-svn: 281811
* [libFuzzer] change trace-pc to use 8-byte guardsKostya Serebryany2016-09-1710-32/+156
| | | | llvm-svn: 281810
* [sanitizer-coverage] change trace-pc to use 8-byte guardsKostya Serebryany2016-09-171-24/+27
| | | | llvm-svn: 281809
* Revert "Don't create a SymbolTable in Function when the LLVMContext discards ↵Mehdi Amini2016-09-171-4/+2
| | | | | | | | | value names (NFC)" This reverts commit r281806. It introduces undefined behavior as an API is returning a reference to the Symtab llvm-svn: 281808
* Don't create a SymbolTable in Function when the LLVMContext discards value ↵Mehdi Amini2016-09-171-2/+4
| | | | | | | | | | | names (NFC) The ValueSymbolTable is used to detect name conflict and rename instructions automatically. This is not needed when the value names are automatically discarded by the LLVMContext. No functional change intended, just saving a little bit of memory. llvm-svn: 281806
* AMDGPU: Use i64 scalar compare instructionsMatt Arsenault2016-09-174-12/+45
| | | | | | VI added eq/ne for i64, so use them. llvm-svn: 281800
* AMDGPU/SI: Fix kernel argument ABI for HSATom Stellard2016-09-161-1/+2
| | | | | | | | | | | | Summary: i8, i16, and f16 values are not extended to 32-bit in the HSA kernel ABI. Reviewers: arsenm Subscribers: arsenm, kzhuravl, wdng, nhaehnle, llvm-commits, yaxunl Differential Revision: https://reviews.llvm.org/D24621 llvm-svn: 281789
* [InstCombine] canonicalize vector select with constant vector condition to ↵Sanjay Patel2016-09-161-0/+39
| | | | | | | | | | | | | | | | | | | | shuffle As discussed on llvm-dev ( http://lists.llvm.org/pipermail/llvm-dev/2016-August/104210.html ): turn a vector select with constant condition operand into a shuffle as a canonicalization step. Shuffles may be easier to reason about in conjunction with other shuffles and insert/extract. Possible known (minor?) regressions from this change are filed as: https://llvm.org/bugs/show_bug.cgi?id=28530 https://llvm.org/bugs/show_bug.cgi?id=28531 https://llvm.org/bugs/show_bug.cgi?id=30371 If something terrible happens to perf after this commit, feel free to revert until a backend fix is in place. Differential Revision: https://reviews.llvm.org/D24279 llvm-svn: 281787
* AMDGPU: Allow some control flow intrinsics to be CSEdMatt Arsenault2016-09-165-27/+80
| | | | | | | | | | | These clean up some unnecessary or instructions in cases with complex loops. In the original testcase I noticed this, the same or with exec was repeated 5 or 6 times in a row. With this only one is emitted or sometimes a copy. llvm-svn: 281786
* [safestack] Fix assertion failure in stack coloring.Evgeniy Stepanov2016-09-161-4/+6
| | | | | | | | | | This is a fix for PR30318. Clang may generate IR where an alloca is already live when entering a BB with lifetime.start. In this case, conservatively extend the alloca lifetime all the way back to the block entry. llvm-svn: 281784
* [RegAllocGreedy] Fix the list of NewVRegs for last chance recoloring.Quentin Colombet2016-09-161-2/+22
| | | | | | | | | | | | | | | | | When trying to recolor a register we may split live-ranges in the process. When we create new live-ranges we will have to process them, but when we move a register from Assign to Split, the allocation is not changed until the whole recoloring session is successful. Therefore, only push the live-ranges that changed from Assign to Split when the recoloring is successful. Same as the previous commit, I was not able to produce a test case that reproduce the problem with in-tree targets. Note: The bug has been here since the recoloring scheme has been added back in r200883 (Feb 2014). llvm-svn: 281783
* [RegAllocGreedy] Fix an assertion and condition when last chance recoloring ↵Quentin Colombet2016-09-161-2/+3
| | | | | | | | | | | | | | | | is used. When last chance recoloring is used, the list of NewVRegs may not be empty when calling selectOrSplitImpl. Indeed, another coloring may have taken place with splitting/spilling in the same recoloring session. Relax an assertion to take this into account and adapt a condition to act as if the NewVRegs were local to this selectOrSplitImpl instance. Unfortunately I am unable to produce a test case for this, I was only able to reproduce the conditions on an out-of-tree target. llvm-svn: 281782
* AMDGPU: Refactor kernel argument loweringTom Stellard2016-09-164-52/+109
| | | | | | | | | | | | | | | | | | | Summary: The main challenge in lowering kernel arguments for AMDGPU is determing the memory type of the argument. The generic calling convention code assumes that only legal register types can be stored in memory, but this is not the case for AMDGPU. This consolidates all the logic AMDGPU uses for deducing memory types into a single function. This will make it much easier to support different ABIs in the future. Reviewers: arsenm Subscribers: arsenm, wdng, nhaehnle, llvm-commits, yaxunl Differential Revision: https://reviews.llvm.org/D24614 llvm-svn: 281781
* AMDGPU: Use SOPK compare instructionsMatt Arsenault2016-09-167-51/+152
| | | | llvm-svn: 281780
* AMDGPU/SI: Add support for triples with the mesa3d operating systemTom Stellard2016-09-167-13/+22
| | | | | | | | | | | | | | Summary: mesa3d will use the same kernel calling convention as amdhsa, but it will handle everything else like the default 'unknown' OS type. Reviewers: arsenm Subscribers: arsenm, llvm-commits, kzhuravl Differential Revision: https://reviews.llvm.org/D22783 llvm-svn: 281779
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