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* [Hexagon] Remove unused .td filesKrzysztof Parzyszek2017-02-107-2572/+0
| | | | llvm-svn: 294775
* [X86] Bitcast subvector before broadcasting it.Ahmed Bougacha2017-02-101-1/+10
| | | | | | | | | | | | | Since r274013, we've been looking through bitcasts on broadcast inputs. In the scalar-folding case (from a load, build_vector, or sc2vec), the input type didn't matter, as we'd simply bitcast the resulting scalar back. However, when broadcasting a 128-bit-lane-aligned element, we create an EXTRACT_SUBVECTOR. Use proper types, by creating an extract_subvector of the original input type. llvm-svn: 294774
* Yet another fix llvm-objdump so it picks a good CPU based for Mach-O files,Kevin Enderby2017-02-101-0/+2
| | | | | | | | | | | in this case for CPU_SUBTYPE_ARM64_ALL. For this cpusubtype it should default to a cyclone CPU to give proper disassembly without a -mcpu= flag. rdar://27767188 llvm-svn: 294771
* GlobalISel: drop lifetime intrinsics during translation.Tim Northover2017-02-101-0/+8
| | | | | | We don't use them yet and they just cause problems. llvm-svn: 294770
* [libFuzzer] Use stoull instead of stol to ensure 64 bits.Marcos Pividori2017-02-101-2/+2
| | | | | | Differential revision: https://reviews.llvm.org/D29831 llvm-svn: 294769
* [ARM] Fix incorrect mask bits in MSR encoding for write_register intrinsicJohn Brawn2017-02-101-10/+6
| | | | | | | | | | | In the encoding of system registers in the M-class MSR instruction the mask bits should be 2 for registers that don't take a _<bits> qualifier (the instruction is unpredictable otherwise), and should also be 2 if the register takes a _<bits> qualifier but it's not present as no _<bits> is an alias for _nzcvq. Differential Revision: https://reviews.llvm.org/D29828 llvm-svn: 294762
* [LV] Remove type restriction for vector phi creationMatthew Simpson2017-02-101-2/+1
| | | | | | | | | We previously only created a vector phi node for an induction variable if its type matched the type of the canonical induction variable. Differential Revision: https://reviews.llvm.org/D29776 llvm-svn: 294755
* [Hexagon] Replace instruction definitions with auto-generated onesKrzysztof Parzyszek2017-02-1037-12829/+48409
| | | | llvm-svn: 294753
* Move some error handling down to MCStreamer.Rafael Espindola2017-02-1011-30/+25
| | | | | | | | | This makes sure we get the same redefinition rules regardless of who is printing (asm parser, codegen) and to what (asm, obj). This fixes an unintentional regression in r293936. llvm-svn: 294752
* [DAGCombine] Allow vector constant folding of any value type before type ↵Simon Pilgrim2017-02-102-1/+6
| | | | | | | | | | | | | | | | legalization The patch comes in 2 parts: 1 - it makes use of the SelectionDAG::NewNodesMustHaveLegalTypes flag to tell when it can safely constant fold illegal types. 2 - it correctly resets SelectionDAG::NewNodesMustHaveLegalTypes at the start of each call to SelectionDAGISel::CodeGenAndEmitDAG so all the pre-legalization stages can make use of it - not just the first basic block that gets handled. Fix for PR30760 Differential Revision: https://reviews.llvm.org/D29568 llvm-svn: 294749
* [X86][SSE] Use SDValue::getConstantOperandVal helper. NFCI.Simon Pilgrim2017-02-101-11/+6
| | | | | | Also reordered an if statement to test low cost comparisons first llvm-svn: 294748
* [X86][SSE] Add support for extracting target constants from BUILD_VECTORSimon Pilgrim2017-02-101-0/+17
| | | | | | | In some cases we call getTargetConstantBitsFromNode for nodes that haven't been lowered from BUILD_VECTOR yet Note: We're getting very close to being able to move most of the constant extraction code from getTargetShuffleMaskIndices into getTargetConstantBitsFromNode llvm-svn: 294746
* [X86][SSE] Add missing comment describing combing to SHUFPS. NFCISimon Pilgrim2017-02-101-0/+2
| | | | llvm-svn: 294745
* add #ifdef, fix compilation error in case LLVM_BUILD_GLOBAL_ISEL=OFFIgor Breger2017-02-101-0/+2
| | | | llvm-svn: 294726
* [X86][GlobalISel] Add general-purpose Register BankIgor Breger2017-02-109-12/+369
| | | | | | | | | | | | | | | | | Summary: [X86][GlobalISel] Add general-purpose Register Bank. Add trivial handling of G_ADD legalization . Add Regestry Bank selection for COPY and G_ADD instructions Reviewers: rovka, zvi, ab, t.p.northover, qcolombet Reviewed By: qcolombet Subscribers: qcolombet, mgorny, dberris, kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D29771 llvm-svn: 294723
* [LoopUnswitch] Remove BFI usage (dead code)Philip Reames2017-02-101-43/+0
| | | | | | | | Chandler mentioned at the last social that the need for BFI in the new pass manager was causing a slight hiccup for this pass. Given this code has been checked in, but off for over a year, it makes sense to just remove it for now. Note that there's nothing wrong with the general idea - it's actually a quite good one - and once we have the infrastructure in place to implement this without the full recompuation on every loop, we absolutely should. llvm-svn: 294715
* [SelectionDAG] Dump the DAG after legalizing vector ops and after the second ↵Craig Topper2017-02-101-0/+6
| | | | | | | | | | | | | | | | | | | | | type legalization Summary: With -debug, we aren't dumping the DAG after legalizing vector ops. In particular, on X86 with AVX1 only, we don't dump the DAG after we split 256-bit integer ops into pairs of 128-bit ADDs since this occurs during vector legalization. I'm only dumping if the legalize vector ops changes something since we don't print anything during legalize vector ops. So this dump shows up right after the first type-legalization dump happens. So if nothing changed this second dump is unnecessary. Having said that though, I think we should probably fix legalize vector ops to log what its doing. Reviewers: RKSimon, eli.friedman, spatel, arsenm, chandlerc Reviewed By: RKSimon Subscribers: wdng, llvm-commits Differential Revision: https://reviews.llvm.org/D29554 llvm-svn: 294711
* Temporarily revert "For X86-64 linux and PPC64 linux align int128 to 16 bytes."Eric Christopher2017-02-102-10/+0
| | | | | | | | | until we can get better TargetMachine::isCompatibleDataLayout to compare - otherwise we can't code generate existing bitcode without a string equality data layout. This reverts commit r294702. llvm-svn: 294709
* For X86-64 linux and PPC64 linux align int128 to 16 bytes.Eric Christopher2017-02-102-0/+10
| | | | | | | | | | | | For other platforms we should find out what they need and likely make the same change, however, a smaller additional change is easier for platforms we know have it specified in the ABI. As part of this rewrite some of the handling in the backends for data layout and update a bunch of testcases. Based on a patch by Simonas Kazlauskas! llvm-svn: 294702
* AMDGPU: Fix trailing whitespaceMatt Arsenault2017-02-105-14/+13
| | | | llvm-svn: 294694
* AMDGPU : Add trap handler support.Wei Ding2017-02-1010-24/+99
| | | | | | Differential Revision: http://reviews.llvm.org/D26010 llvm-svn: 294692
* [AMDGPU] Override PSet for M0Stanislav Mekhanoshin2017-02-102-0/+10
| | | | | | | | | | | | This change returns empty PSet list for M0 register. Otherwise its PSet as defined by tablegen is SReg_32. This results in incorrect register pressure calculation every time an instruction uses M0. Such uses count as SReg_32 PSet and inadequately increase pressure on SGPRs. Differential Revision: https://reviews.llvm.org/D29798 llvm-svn: 294691
* [CMake] Fix pthread handling for out-of-tree buildsEric Fiselier2017-02-104-5/+5
| | | | | | | | | | | | | | | LLVM defines `PTHREAD_LIB` which is used by AddLLVM.cmake and various projects to correctly link the threading library when needed. Unfortunately `PTHREAD_LIB` is defined by LLVM's `config-ix.cmake` file which isn't installed and therefore can't be used when configuring out-of-tree builds. This causes such builds to fail since `pthread` isn't being correctly linked. This patch attempts to fix that problem by renaming and exporting `LLVM_PTHREAD_LIB` as part of`LLVMConfig.cmake`. I renamed `PTHREAD_LIB` because It seemed likely to cause collisions with downstream users of `LLVMConfig.cmake`. llvm-svn: 294690
* [libFuzzer] Export external functions on tests.Marcos Pividori2017-02-101-0/+12
| | | | | | | | | | | | | We need to export external functions so they are found when calling GetProcAddress() on Windows. But we can't use `__declspec(dllexport)` because we want the targets to be completely independent from the fuzz engines and don't depend on other header files. Also, we don't want to include platform specific code managed with conditional macros. So, the solution is to add the exported symbols with linker flags in cmake. Differential revision: https://reviews.llvm.org/D29752 llvm-svn: 294688
* [libFuzzer] Use dynamic loading for External Functions on Windows.Marcos Pividori2017-02-102-1/+61
| | | | | | | | | | | | | | | | | | | Replace weak aliases with dynamic loading. Weak aliases were generating some problems when linking for MT on Windows. For MT, compiler-rt's libraries are statically linked to the main executable the same than libFuzzer, so if we use weak aliases, we are providing two different default implementations for the same weak function and the linker fails. In this diff I re implement ExternalFunctions() using dynamic loading, so it works in both cases (MD and MT). Also, dynamic loading is simpler, since we are not defining any auxiliary external function, and we don't need to deal with weak aliases. This is equivalent to the implementation using dlsym(RTLD_DEFAULT, FnName) for Posix. Differential revision: https://reviews.llvm.org/D29751 llvm-svn: 294687
* [MC] Fix some Clang-tidy modernize and Include What You Use warnings; other ↵Eugene Zelenko2017-02-1010-86/+139
| | | | | | minor fixes (NFC). llvm-svn: 294685
* [WebAssembly] Pass an MCContext to WebAssemblyMCCodeEmitter. NFC.Dan Gohman2017-02-103-6/+10
| | | | llvm-svn: 294679
* Fix syntax errorMatthias Braun2017-02-101-2/+2
| | | | llvm-svn: 294678
* ARMSubtarget.h: Change to one line per enum element; NFCMatthias Braun2017-02-101-9/+56
| | | | | | | Change syntax to have enum elements sorted alphabetically and one per line as that is more merge/cherry pick friendly. llvm-svn: 294677
* Add an additional set of braces to deal with subobject initialization.Eric Christopher2017-02-101-1/+1
| | | | llvm-svn: 294674
* [PM] Add Argument Promotion to the pass pipeline.Chandler Carruth2017-02-091-0/+9
| | | | | | | | | | | This needs explicit requires of the optimization remark emission before loop pass pipelines containing LICM as we no longer get it from the inliner -- Argument Promotion may invalidate it. Technically the inliner could also have broken this, but it never came up in testing. Differential Revision: https://reviews.llvm.org/D29595 llvm-svn: 294670
* [PM] Port ArgumentPromotion to the new pass manager.Chandler Carruth2017-02-093-29/+88
| | | | | | | | | | | | | | | Now that the call graph supports efficient replacement of a function and spurious reference edges, we can port ArgumentPromotion to the new pass manager very easily. The old PM-specific bits are sunk into callbacks that the new PM simply doesn't use. Unlike the old PM, the new PM simply does argument promotion and afterward does the update to LCG reflecting the promoted function. Differential Revision: https://reviews.llvm.org/D29580 llvm-svn: 294667
* WholeProgramDevirt: Check that VCP candidate functions are defined before ↵Peter Collingbourne2017-02-091-5/+5
| | | | | | | | evaluating them. This was crashing before. llvm-svn: 294666
* [PM/LCG] Teach LCG to support spurious reference edges.Chandler Carruth2017-02-091-1/+8
| | | | | | | | | | | | | | | | | | Somewhat amazingly, this only requires teaching it to clean them up when deleting a dead function from the graph. And we already have exactly the necessary data structures to do that in the parent RefSCCs. This allows ArgPromote to work in a much simpler way be merely letting reference edges linger in the graph after the causing IR is deleted. We will clean up these edges when we run any function pass over the IR, but don't remove them eagerly. This avoids all of the quadratic update issues both in the current pass manager and in my previous attempt with the new pass manager. Differential Revision: https://reviews.llvm.org/D29579 llvm-svn: 294663
* [ARM] Add support for armv7ve triple in llvm (PR31358).George Burgess IV2017-02-094-13/+17
| | | | | | | | | | | | | | | Gcc supports target armv7ve which is armv7-a with virtualization extensions. This change adds support for this in llvm for gcc compatibility. Also remove redundant FeatureHWDiv, FeatureHWDivARM for a few models as this is specified automatically by FeatureVirtualization. Patch by Manoj Gupta. Differential Revision: https://reviews.llvm.org/D29472 llvm-svn: 294661
* [PM/LCG] Teach the LazyCallGraph how to replace a function withoutChandler Carruth2017-02-093-196/+218
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | disturbing the graph or having to update edges. This is motivated by porting argument promotion to the new pass manager. Because of how LLVM IR Function objects work, in order to change their signature a new object needs to be created. This is efficient and straight forward in the IR but previously was very hard to implement in LCG. We could easily replace the function a node in the graph represents. The challenging part is how to handle updating the edges in the graph. LCG previously used an edge to a raw function to represent a node that had not yet been scanned for calls and references. This was the core of its laziness. However, that model causes this kind of update to be very hard: 1) The keys to lookup an edge need to be `Function*`s that would all need to be updated when we update the node. 2) There will be some unknown number of edges that haven't transitioned from `Function*` edges to `Node*` edges. All of this complexity isn't necessary. Instead, we can always build a node around any function, always pointing edges at it and always using it as the key to lookup an edge. To maintain the laziness, we need to sink the *edges* of a node into a secondary object and explicitly model transitioning a node from empty to populated by scanning the function. This design seems much cleaner in a number of ways, but importantly there is now exactly *one* place where the `Function*` has to be updated! Some other cleanups that fall out of this include having something to model the *entry* edges more accurately. Rather than hand rolling parts of the node in the graph itself, we have an explicit `EdgeSequence` object that gives us exactly the functionality needed. We also have a consistent place to define the edge iterators and can use them for both the entry edges and the internal edges of the graph. The API used to model the separation between a node and its edges is intentionally very thin as most clients are expected to deal with nodes that have populated edges. We model this exactly as an optional does with an additional method to populate the edges when that is a reasonable thing for a client to do. This is based on API design suggestions from Richard Smith and David Blaikie, credit goes to them for helping pick how to model this without it being either too explicit or too implicit. The patch is somewhat noisy due to shifting around iterator types and new syntax for walking the edges of a node, but most of the functionality change is in the `Edge`, `EdgeSequence`, and `Node` types. Differential Revision: https://reviews.llvm.org/D29577 llvm-svn: 294653
* [WebAssembly] Refactor void return peephole using MaybeRewriteToFallthrough. ↵Dan Gohman2017-02-091-13/+15
| | | | | | NFC. llvm-svn: 294652
* [InstCombine] allow (X * C2) << C1 --> X * (C2 << C1) for vectorsSanjay Patel2017-02-091-13/+12
| | | | | | | | | | This fold already existed for vectors but only when 'C1' was a splat constant (but 'C2' could be any constant). There were no tests for any vector constants, so I'm adding a test that shows non-splat constants for both operands. llvm-svn: 294650
* De-duplicate some code for creating an AARGetter suitable for the legacy PM.Peter Collingbourne2017-02-093-35/+4
| | | | | | | | I'm about to use this in a couple more places. Differential Revision: https://reviews.llvm.org/D29793 llvm-svn: 294648
* Fix build break from r294633.Adrian McCarthy2017-02-091-3/+3
| | | | llvm-svn: 294642
* [X86] Remove duplicate call to getValueType. NFCI.Simon Pilgrim2017-02-091-4/+3
| | | | llvm-svn: 294640
* X86: Introduce relocImm-based patterns for cmp.Peter Collingbourne2017-02-093-0/+47
| | | | | | Differential Revision: https://reviews.llvm.org/D28690 llvm-svn: 294636
* AMDGPU: Add pass to expand memcpy/memmove/memsetMatt Arsenault2017-02-095-4/+136
| | | | llvm-svn: 294635
* X86: Teach X86InstrInfo::analyzeCompare to recognize compares of symbols.Peter Collingbourne2017-02-091-17/+22
| | | | | | | | | | | | | | | This requires that we communicate to X86InstrInfo::optimizeCompareInstr that the second operand is neither a register nor an immediate. The way we do that is by setting CmpMask to zero. Note that there were already instructions where the second operand was not a register nor an immediate, namely X86::SUB*rm, so also set CmpMask to zero for those instructions. This seems like a latent bug, but I was unable to trigger it. Differential Revision: https://reviews.llvm.org/D28621 llvm-svn: 294634
* Introduce NativeRawSymbol for PDB reading.Adrian McCarthy2017-02-092-0/+701
| | | | | | | | | | This is a stub for a new concrete implementation of IPDBRawSymbol. Nothing uses this uses this implementation yet. My plan is to locally switch lldb-pdbdump from the DIA reader to the Native one and flesh out the implementations of these method stubs in the order they're needed. llvm-svn: 294633
* [LoadCombine] Fix combining of loads which span an aliasing store.Michael J. Spencer2017-02-091-1/+5
| | | | | | | | Fixes PR31517 Differential Revision: https://reviews.llvm.org/D28922 llvm-svn: 294632
* Rename LowerTypeTestsSummaryAction to PassSummaryAction. NFCI.Peter Collingbourne2017-02-093-24/+21
| | | | | | | | | I intend to use the same type with the same semantics in the WholeProgramDevirt pass. Differential Revision: https://reviews.llvm.org/D29746 llvm-svn: 294629
* [InstCombine] use m_APInt to allow demanded bits analysis on splat constantsSanjay Patel2017-02-091-10/+13
| | | | llvm-svn: 294628
* [AMDGPU] Calculate number of min/max SGPRs/VGPRs for WavesPerEU instead of ↵Konstantin Zhuravlyov2017-02-092-68/+31
| | | | | | | | using switch statement Differential Revision: https://reviews.llvm.org/D29741 llvm-svn: 294627
* Drop graph_ prefixDaniel Berlin2017-02-096-10/+10
| | | | llvm-svn: 294621
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