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* [CGP] Relax a bit restriction for optimizeMemoryInst to extend scopeSerguei Katkov2017-07-111-2/+5
| | | | | | | | | | | | | | | | | | CodeGenPrepare::optimizeMemoryInst contains a check that we do nothing if all instructions combining the address for memory instruction is in the same block as memory instruction itself. However if any of these instruction are placed after memory instruction then address calculation will not be folded to memory instruction. The added test case shows an example. Reviewers: loladiro, spatel, efriedma Reviewed By: efriedma Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D34862 llvm-svn: 307628
* fix typos in comments; NFCHiroshi Inoue2017-07-112-2/+2
| | | | llvm-svn: 307626
* [PM/ThinLTO] Fix PR33536, a bug where the ThinLTO bitcode writer wasChandler Carruth2017-07-111-1/+2
| | | | | | | | | | | | | querying for analysis results on a function declaration rather than a definition. The only reason this worked previously is by chance -- because the way we got alias analysis results with the legacy PM, we happened to not compute a dominator tree and so we happened to not hit an assert even though it didn't make any real sense. Now we bail out before trying to compute alias analysis so that we don't hit these asserts. llvm-svn: 307625
* [PowerPC] fix latency for simple integer instructions in POWER9 schedulerHiroshi Inoue2017-07-111-1/+1
| | | | | | | | | In the POWER9 instruction scheduler, SchedWriteRes for the simple integer instructions are misconfigured to use that of (costly) DFU instructions. This results in surprisingly long instruction latency estimation and causes misbehavior in some optimizers such as if-conversion. Differential Revision: https://reviews.llvm.org/D34869 llvm-svn: 307624
* [PowerPC] avoid redundant analysis while lowering an immediate; NFCHiroshi Inoue2017-07-111-2/+8
| | | | | | | | | | This patch reduces compilation time by avoiding redundant analysis while selecting instructions to create an immediate. If the instruction count required to create the input number without rotate is 2, we do not need further analysis to find a shorter instruction sequence with rotate; rotate + load constant cannot be done by 1 instruction (i.e. getInt64CountDirectnever return 0). This patch should not change functionality. Differential Revision: https://reviews.llvm.org/D34986 llvm-svn: 307623
* [AVR] Remove a few very old TODOs that don't have enough context to understandDylan McKay2017-07-112-3/+4
| | | | llvm-svn: 307622
* [AVR] Rename 'ZREGS' to 'ZREG'Dylan McKay2017-07-113-16/+13
| | | | | | It will only ever contain one register. llvm-svn: 307620
* [AVR] Rename 'AVRTiny' to 'Tiny'Dylan McKay2017-07-112-13/+12
| | | | llvm-svn: 307619
* [AVR] Use the generic branch relaxerDylan McKay2017-07-113-5/+77
| | | | llvm-svn: 307617
* Whitespace.NAKAMURA Takumi2017-07-111-1/+1
| | | | llvm-svn: 307614
* Revert r307581, "Avoid doing conservative phi checks in ↵NAKAMURA Takumi2017-07-112-12/+8
| | | | | | | | aliasSameBasePointerGEPs() if no phis have been visited yet." It broke stage2 tests in selfhosting. llvm-svn: 307613
* [WebAssembly] Fix use of cast vs dyn_castSam Clegg2017-07-111-15/+7
| | | | | | Differential Revision: https://reviews.llvm.org/D35233 llvm-svn: 307612
* [lld/pdb] Create an empty public symbol record stream.Zachary Turner2017-07-105-16/+127
| | | | | | | | | | | | | | This is part of the continuing effort to increase parity between LLD and MSVC PDBs. link still doesn't like our PDBs, so the most obvious thing to check was whether adding an empty publics stream would get it to do something else. It still fails in the same way but at least this removes one more variable from the equation. The next logical step would be to try creating an empty globals stream. Differential Revision: https://reviews.llvm.org/D35224 llvm-svn: 307598
* Doxygen formatting. NFCIJoel Jones2017-07-103-6/+15
| | | | llvm-svn: 307597
* Revert "[DAG] Improve Aliasing of operations to static alloca"Matthias Braun2017-07-101-14/+6
| | | | | | | | | Reverting as it breaks tramp3d-v4 in the llvm test-suite. I added some comments to https://reviews.llvm.org/D33345 about it. This reverts commit r307546. llvm-svn: 307589
* [ConstantHoisting] Remove dupliate logic in constant hoistingLeo Li2017-07-102-34/+11
| | | | | | | | | | | | | | | | | | | | | Summary: As metioned in https://reviews.llvm.org/D34576, checkings in `collectConstantCandidates` can be replaced by using `llvm::canReplaceOperandWithVariable`. The only special case is that `collectConstantCandidates` return false for all `IntrinsicInst` but it is safe for us to collect constant candidates from `IntrinsicInst`. Reviewers: pirama, efriedma, srhines Reviewed By: efriedma Subscribers: llvm-commits, javed.absar Differential Revision: https://reviews.llvm.org/D34921 llvm-svn: 307587
* [NewGVN] Simplify a lambda a little bit. NFCI.Davide Italiano2017-07-101-3/+1
| | | | llvm-svn: 307586
* Add DAG argument to canMergeStoresTo NFC.Nirav Dave2017-07-106-12/+19
| | | | llvm-svn: 307583
* [Hexagon] Convert typed ISD opcodes to generic ones, NFCKrzysztof Parzyszek2017-07-103-58/+43
| | | | llvm-svn: 307582
* Avoid doing conservative phi checks in aliasSameBasePointerGEPs() if no phis ↵Farhana Aleen2017-07-102-8/+12
| | | | | | | | | | | | have been visited yet. Reviewers: Daniel Berlin Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D34478 llvm-svn: 307581
* [Hexagon] Remove unused ISD opcodes, NFCKrzysztof Parzyszek2017-07-103-97/+0
| | | | llvm-svn: 307580
* Use DenseMap instead std::map for GVSummaryMapTy.Dehao Chen2017-07-101-1/+1
| | | | | | | | | | | | | | Summary: This speeds-up thin-link by ~47% for large programs. Reviewers: tejohnson Reviewed By: tejohnson Subscribers: sanjoy, llvm-commits, mehdi_amini Differential Revision: https://reviews.llvm.org/D35148 llvm-svn: 307578
* AMDGPU: Allow SIShrinkInstructions to fold FrameIndexesMatt Arsenault2017-07-101-0/+4
| | | | llvm-svn: 307576
* AMDGPU: Allow SIShrinkInstructions to work in non-SSAMatt Arsenault2017-07-101-24/+33
| | | | | | | | Immediates can be folded as long as the immediate is a vreg. Also undo commuting instructions if it didn't fold an immediate. llvm-svn: 307575
* AMDGPU: Remove unnecessary check for constant operandsMatt Arsenault2017-07-101-5/+0
| | | | | | | | | | An instruction that has an immediate operand can't reach this point. This is only called for a freshly shrunk instruction, which prevously couldn't have had a literal constant operand. This was also not conservative enough since it woudl also have had to filter other constant-like inputs like frame indexes. llvm-svn: 307574
* AMDGPU: Do not test for SI in getIsaVersionKonstantin Zhuravlyov2017-07-101-1/+1
| | | | | | SI is being tested by isa version in the first two if statements of the function. llvm-svn: 307573
* [Hexagon] Fix check for HMOTF_ConstExtend operand flagKrzysztof Parzyszek2017-07-103-19/+14
| | | | | | This fixes https://llvm.org/PR33718. llvm-svn: 307566
* [WebAssembly] Use the correct size for MCFillFragmentSam Clegg2017-07-101-1/+1
| | | | | | | | | | | Summary: When implementing MCFillFragment, use the size of the fragment, rather than the size of the section. Patch by Dan Gohman Differential Revision: https://reviews.llvm.org/D35090 llvm-svn: 307565
* [Hexagon] Handle Hexagon-specific machine operand target flags in MIRKrzysztof Parzyszek2017-07-103-4/+63
| | | | llvm-svn: 307564
* [PPC CodeGen] Expand the bitreverse.i64 intrinsic.Tony Jiang2017-07-102-0/+120
| | | | | | | Differential Revision: https://reviews.llvm.org/D34908 Fix PR: https://bugs.llvm.org/show_bug.cgi?id=33093 llvm-svn: 307563
* Fix invalid cast in instcombine UMul/ZExt idiomSerge Guelton2017-07-101-6/+7
| | | | | | | | | | | Fixes https://bugs.llvm.org/show_bug.cgi?id=25454 Do not assume IRBuilder creates Instruction where it can create Value. Do not assume idiom operands are constant, leave generalisation ot the IRBuilder. Differential Revision: https://reviews.llvm.org/D35114 llvm-svn: 307554
* [PowerPC] Reduce register pressure by not materializing a constant just for ↵Lei Huang2017-07-101-4/+9
| | | | | | | | | | | | | | | | | | | | | | | | use as an index register for X-Form loads/stores. For this example: float test (int *arr) { return arr[2]; } We currently generate the following code: li r4, 8 lxsiwax f0, r3, r4 xscvsxdsp f1, f0 With this patch, we will now generate: addi r3, r3, 8 lxsiwax f0, 0, r3 xscvsxdsp f1, f0 Originally reported in: https://bugs.llvm.org/show_bug.cgi?id=27204 Differential Revision: https://reviews.llvm.org/D35027 llvm-svn: 307553
* [X86] Model 256-bit AVX instructions in the AMD Jaguar scheduler Part-1 ↵Andrew V. Tischenko2017-07-101-0/+77
| | | | | | | | | | | (PR28573). The new version of the model is definitely faster. Differential Revision: https://reviews.llvm.org/D35198 llvm-svn: 307552
* [DAG] Improve Aliasing of operations to static allocaNirav Dave2017-07-101-6/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Memory accesses offset from frame indices may alias, e.g., we may merge write from function arguments passed on the stack when they are contiguous. As a result, when checking aliasing, we consider the underlying frame index's offset from the stack pointer. Static allocs are realized as stack objects in SelectionDAG, but its offset is not set until post-DAG causing DAGCombiner's alias check to consider access to static allocas to frequently alias. Modify isAlias to consider access between static allocas and access from other frame objects to be considered aliasing. Many test changes are included here. Most are fixes for tests which indirectly relied on our aliasing ability and needed to be modified to preserve their original intent. The remaining tests have minor improvements due to relaxed ordering. The exception is CodeGen/X86/2011-10-19-widen_vselect.ll which has a minor degradation dispite though the pre-legalized DAG is improved. Reviewers: rnk, mkuper, jonpa, hfinkel, uweigand Reviewed By: rnk Subscribers: sdardis, nemanjai, javed.absar, llvm-commits Differential Revision: https://reviews.llvm.org/D33345 llvm-svn: 307546
* [LoopUnrollRuntime] Remove strict assert about VMap requirementAnna Thomas2017-07-101-4/+3
| | | | | | | | | | | | | When unrolling under multiple exits which is under off-by-default option, the assert that checks for VMap entry in loop exit values is too strong. (assert if VMap entry did not exist, the value should be a constant). However, values derived from constants or from values outside loop, does not have a VMap entry too. Removed the assert and added a testcase showcasing the property for non-constant values. llvm-svn: 307542
* fix typos in comments and error messages; NFCHiroshi Inoue2017-07-105-8/+8
| | | | llvm-svn: 307533
* [PM] Enable registration of out-of-tree passes with PassBuilderPhilip Pfaffe2017-07-101-34/+187
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: This patch adds a callback registration API to the PassBuilder, enabling registering out-of-tree passes with it. Through the Callback API, callers may register callbacks with the various stages at which passes are added into pass managers, including parsing of a pass pipeline as well as at extension points within the default -O pipelines. Registering utilities like `require<>` and `invalidate<>` needs to be handled manually by the caller, but a helper is provided. Additionally, adding passes at pipeline extension points is exposed through the opt tool. This patch adds a `-passes-ep-X` commandline option for every extension point X, which opt parses into pipelines inserted into that extension point. Reviewers: chandlerc Reviewed By: chandlerc Subscribers: lksbhm, grosser, davide, mehdi_amini, llvm-commits, mgorny Differential Revision: https://reviews.llvm.org/D33464 llvm-svn: 307532
* [ARM] Tidy up ARMBaseRegisterInfo implementation. NFCJaved Absar2017-07-101-11/+8
| | | | | | | Clean up ARMBaseRegisterInfo implementation a bit. Differential Revision: https://reviews.llvm.org/D35116 llvm-svn: 307531
* [DWARF] - Rename variable. NFC.George Rimar2017-07-101-3/+3
| | | | | | | | | | | | Variable was called 'Name' and contained text name of relocation type. Problem was that outside of this error handling scope we already have different 'Name' variable that contains section name. Change helps to avoid confusion. llvm-svn: 307530
* This patch completely replaces the scheduling information for the ↵Gadi Haber2017-07-101-30/+2442
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | SandyBridge architecture target by modifying the file X86SchedSandyBridge.td located under the X86 Target. The SandyBridge architects have provided us with a more accurate information about each instruction latency, number of uOPs and used ports and I used it to replace the existing estimated SNB instructions scheduling and to add missing scheduling information. Please note that the patch extensively affects the X86 MC instr scheduling for SNB. Also note that this patch will be followed by additional patches for the remaining target architectures HSW, IVB, BDW, SKL and SKX. The updated and extended information about each instruction includes the following details: •static latency of the instruction •number of uOps from which the instruction consists of •all ports used by the instruction's' uOPs For example, the following code dictates that instructions, ADC64mr, ADC8mr, SBB64mr, SBB8mr have a static latency of 9 cycles. Each of these instructions is decoded into 6 micro operations which use ports 4, ports 2 or 3 and port 0 and ports 0 or 1 or 5: def SBWriteResGroup94 : SchedWriteRes<[SBPort4,SBPort23,SBPort0,SBPort015]> { let Latency = 9; let NumMicroOps = 6; let ResourceCycles = [1,2,2,1]; } def: InstRW<[SBWriteResGroup94], (instregex "ADC64mr")>; def: InstRW<[SBWriteResGroup94], (instregex "ADC8mr")>; def: InstRW<[SBWriteResGroup94], (instregex "SBB64mr")>; def: InstRW<[SBWriteResGroup94], (instregex "SBB8mr")>; Note that apart for the header, most of the X86SchedSandyBridge.td file was generated by a script. Reviewers: zvi, chandlerc, RKSimon, m_zuckerman, craig.topper, igorb Differential Revision: https://reviews.llvm.org/D35019#inline-304691 llvm-svn: 307529
* [DWARF] - Remove unused variables. NFC.George Rimar2017-07-101-6/+2
| | | | llvm-svn: 307528
* [GlobalISel][X86] Support G_LOAD/G_STORE i1.Igor Breger2017-07-101-0/+2
| | | | | | | | | | | | | | Summary: Support G_LOAD/G_STORE i1. Reviewers: zvi, guyblank Reviewed By: guyblank Subscribers: rovka, kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D35178 llvm-svn: 307527
* [GlobalISel][X86] extend G_ZEXT support.Igor Breger2017-07-102-24/+29
| | | | | | | | | | | | | | | | | Summary: Mark G_ZEXT/G_SEXT i1 to i8/i16, i8 to i16 as legal. Support G_ZEXT i1 to i8/i16 instruction selection ( C++ code). This patch requred to support G_LOAD/G_STORE i1. Reviewers: zvi, guyblank Reviewed By: guyblank Subscribers: rovka, llvm-commits, kristof.beyls Differential Revision: https://reviews.llvm.org/D35177 llvm-svn: 307526
* fix formatting; NFCHiroshi Inoue2017-07-101-2/+2
| | | | llvm-svn: 307523
* [X86] Fix typo in comment. NFCCraig Topper2017-07-101-1/+1
| | | | llvm-svn: 307522
* [ArgumentPromotion] Change use of removed argument in llvm.dbg.value to undefMikael Holmen2017-07-101-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | Summary: This solves PR33641. When removing a dead argument we must also handle possibly existing calls to llvm.dbg.value that use the removed argument. Now we change the use of the otherwise dead argument to an undef for some other pass to cleanup later. If the calls are left untouched, they will later on cause errors: "function-local metadata used in wrong function" since the ArgumentPromotion rewrites the code by creating a new function with the wanted signature, but the metadata is not recreated so the new function may then erroneously use metadata from the old function. Reviewers: mstorsjo, rnk, arsenm Reviewed By: rnk Subscribers: wdng, llvm-commits Differential Revision: https://reviews.llvm.org/D34874 llvm-svn: 307521
* [X86] Remove asserts from getX86CpuIDAndInfo/getX86CpuIDAndInfoEx. Restore ↵Craig Topper2017-07-101-7/+10
| | | | | | | | | | past behavior of returning an unsupported indication to the caller instead. These asserts could only occur if we fail to properly detect the compiler, but an assert is not a good way to do that because it doesn't work in release builds. I wonder if we could use #error? llvm-svn: 307520
* llvm-profdata: Reduce memory usage by using Error callback rather than memberDavid Blaikie2017-07-102-33/+40
| | | | | | | | | | | | | | | | Reduces llvm-profdata memory usage on a large profile from 7.8GB to 5.1GB. The ProfData API now supports reporting all the errors/warnings rather than only the first, though llvm-profdata ignores everything after the first for now to preserve existing behavior. (if there's a desire for other behavior, happy to implement that - but might be as well left for a separate patch) Reviewers: davidxl Differential Revision: https://reviews.llvm.org/D35149 llvm-svn: 307516
* [X86] Relax an assertion when legalizing vector types.Davide Italiano2017-07-091-0/+4
| | | | | | | | | | | | | | WidenVSELECTAndMask can fold (and it folds in this case) so we get a BUILD_VECTOR of constants as mask. convertMask() seems to work fine when the input is a vector of constants, and we still need to call it to extend/add elements at the end. but the current code just asserts on anything but a SETCC or AND/OR/XOR of 2xSETCC. This change was discussed briefly with Simon Pilgrim, who also suggests we might consider dropping this assertion in the future. Fixes PR33715. llvm-svn: 307508
* [X86] Allow GHC calling convention to use YMM and ZMM registersSimon Pilgrim2017-07-091-1/+9
| | | | | | | | | | GHC 8.4 will know how to use YMM and ZMM registers for calls. Submitted on behalf of @bgamari (Ben Gamari) Differential Revision: https://reviews.llvm.org/D34854 llvm-svn: 307504
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