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| author | Hiroshi Inoue <inouehrs@jp.ibm.com> | 2017-07-11 05:37:16 +0000 |
|---|---|---|
| committer | Hiroshi Inoue <inouehrs@jp.ibm.com> | 2017-07-11 05:37:16 +0000 |
| commit | df6a0fb8a7921188148fd853b22526c74ebcc866 (patch) | |
| tree | 6beefa99fbfc565b2fd6d7deee37935aabd8fac5 /llvm/lib | |
| parent | f55ee1b4766869c1a60cb35a000960d73ba88349 (diff) | |
| download | bcm5719-llvm-df6a0fb8a7921188148fd853b22526c74ebcc866.tar.gz bcm5719-llvm-df6a0fb8a7921188148fd853b22526c74ebcc866.zip | |
[PowerPC] fix latency for simple integer instructions in POWER9 scheduler
In the POWER9 instruction scheduler, SchedWriteRes for the simple integer instructions are misconfigured to use that of (costly) DFU instructions.
This results in surprisingly long instruction latency estimation and causes misbehavior in some optimizers such as if-conversion.
Differential Revision: https://reviews.llvm.org/D34869
llvm-svn: 307624
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/Target/PowerPC/PPCScheduleP9.td | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/llvm/lib/Target/PowerPC/PPCScheduleP9.td b/llvm/lib/Target/PowerPC/PPCScheduleP9.td index a9c1bd78b05..3de2aadb01b 100644 --- a/llvm/lib/Target/PowerPC/PPCScheduleP9.td +++ b/llvm/lib/Target/PowerPC/PPCScheduleP9.td @@ -260,7 +260,7 @@ let SchedModel = P9Model in { // ***************** Defining Itinerary Class Resources ***************** - def : ItinRW<[P9_DFU_76C, IP_EXEC_1C, DISP_1C, DISP_1C], [IIC_IntSimple, + def : ItinRW<[P9_ALU_2C, IP_EXEC_1C, DISP_1C, DISP_1C], [IIC_IntSimple, IIC_IntGeneral]>; def : ItinRW<[P9_ALU_2C, IP_EXEC_1C, DISP_1C, DISP_1C, DISP_1C], |
