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* [Support] Add a version of fs::make_absolute with a custom CWD.Benjamin Kramer2015-10-051-2/+15
| | | | | | This will be used soon from clang. llvm-svn: 249309
* Fix pr24486.Rafael Espindola2015-10-0521-70/+85
| | | | | | | | | | | | | | | | | | This extends the work done in r233995 so that now getFragment (in addition to getSection) also works for variable symbols. With that the existing logic to decide if a-b can be computed works even if a or b are variables. Given that, the expression evaluation can avoid expanding variables as aggressively and that in turn lets the relocation code see the original variable. In order for this to work with the asm streamer, there is now a dummy fragment per section. It is used to assign a section to a symbol when no other fragment exists. This patch is a joint work by Maxim Ostapenko andy myself. llvm-svn: 249303
* [SelectionDAGBuilder] Remove dead codeDavid Majnemer2015-10-041-1/+1
| | | | | | We already check for LandingPadInst two lines above. llvm-svn: 249280
* Remove unused private field introduced by r249270.Teresa Johnson2015-10-041-5/+2
| | | | llvm-svn: 249277
* Support for function summary index bitcode sections and files.Teresa Johnson2015-10-047-41/+1077
| | | | | | | | | | | | | | | | | | | | | | | | | | Summary: The bitcode format is described in this document: https://drive.google.com/file/d/0B036uwnWM6RWdnBLakxmeDdOeXc/view For more info on ThinLTO see: https://sites.google.com/site/llvmthinlto The first customer is ThinLTO, however the data structures are designed and named more generally based on prior feedback. There are a few comments regarding how certain interfaces are used by ThinLTO, and the options added here to gold currently have ThinLTO-specific names as the behavior they provoke is currently ThinLTO-specific. This patch includes support for generating per-module function indexes, the combined index file via the gold plugin, and several tests (more are included with the associated clang patch D11908). Reviewers: dexonsmith, davidxl, joker.eph Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D13107 llvm-svn: 249270
* [SPARCv9] Add support for the rdpr/wrpr instructions.Joerg Sonnenberger2015-10-044-0/+131
| | | | llvm-svn: 249262
* AVX512: Implemented encoding and intrinsics for VPERMILPS/PD instructions.Igor Breger2015-10-044-61/+102
| | | | | | | | Added tests for intrinsics and encoding. Differential Revision: http://reviews.llvm.org/D12690 llvm-svn: 249261
* [WinEH] Permit branch folding in the face of funcletsDavid Majnemer2015-10-044-84/+135
| | | | | | | | Track which basic blocks belong to which funclets. Permit branch folding to fire but only if it can prove that doing so will not cause code in one funclet to be reused in another. llvm-svn: 249257
* Fix typo in READMEJeroen Ketema2015-10-041-1/+1
| | | | llvm-svn: 249253
* [DAGCombiner] Generalize FADD constant combines to work with vectorsSimon Pilgrim2015-10-031-16/+17
| | | | | | | | Updated the FADD combines to work with vectors as well as scalars. Differential Revision: http://reviews.llvm.org/D13416 llvm-svn: 249251
* include equal sign in debug equations; NFCSanjay Patel2015-10-031-2/+2
| | | | llvm-svn: 249248
* [X86] Lower SEXTLOAD using SIGN_EXTEND_VECTOR_INREG. NCI.Simon Pilgrim2015-10-031-22/+5
| | | | | | The custom lowering in LowerExtendedLoad is doing the equivalent shuffle, so make use of existing lowering code to reduce duplication. llvm-svn: 249243
* Move registerSection out of line and reduce #includes. NFC.Rafael Espindola2015-10-031-0/+8
| | | | llvm-svn: 249241
* [DAGCombiner] Merge SIGN_EXTEND_INREG vector constant folding methods. NCI.Simon Pilgrim2015-10-032-26/+6
| | | | | | | | | | visitSIGN_EXTEND_INREG calls SelectionDAG::getNode to constant fold scalar constants but handles vector constants itself, despite getNode being capable of dealing with them. This required a minor change to the getNode implementation to actually deal with cases where the scalars of a BUILD_VECTOR were wider integers than the vector type - which was the only extra ability of the visitSIGN_EXTEND_INREG implementation. No codegen intended and all existing tests remain the same. llvm-svn: 249236
* [libFuzzer] trying to fix at-exit hangKostya Serebryany2015-10-031-1/+1
| | | | llvm-svn: 249231
* [WebAssembly] Implement the remaining conversion operations.Dan Gohman2015-10-031-31/+54
| | | | | | | This is a temporary assembly syntax that will likely evolve along with broader upcoming syntax changes. llvm-svn: 249225
* Use early return. NFC.Rafael Espindola2015-10-031-12/+12
| | | | llvm-svn: 249224
* Try to appease MSVC, NFCI.Sanjoy Das2015-10-031-90/+91
| | | | | | | | This time by lifting the lambda's in `createNodeFromSelectLikePHI` to the file scope. Looks like there are differences in capture rules between clang and MSVC? llvm-svn: 249222
* AMDGPU/SI: Remove unused tablegen multiclassTom Stellard2015-10-031-16/+0
| | | | | | | | | | Reviewers: arsenm Subscribers: arsenm, llvm-commits Differential Revision: http://reviews.llvm.org/D13395 llvm-svn: 249221
* Disallow assigning symbol a null section.Rafael Espindola2015-10-034-14/+2
| | | | | | | They are constructed without one and they can't go back, so this was effectively dead code. llvm-svn: 249220
* Try to appease the MSVC bots, NFCI.Sanjoy Das2015-10-031-1/+1
| | | | llvm-svn: 249219
* [WebAssembly] Rename setlocal to set_local to match the spec.Dan Gohman2015-10-031-1/+1
| | | | llvm-svn: 249218
* Try to appease the MSVC bots, NFC.Sanjoy Das2015-10-021-1/+2
| | | | llvm-svn: 249216
* [libFuzzer] make LLVMFuzzerTestOneInput (the fuzzer target function) return ↵Kostya Serebryany2015-10-0220-33/+62
| | | | | | int instead of void. The actual return value is not *yet* used (and expected to be 0). This change is API breaking, so the fuzzers will need to be updated. llvm-svn: 249214
* [SCEV] Recognize simple br-phi patternsSanjoy Das2015-10-021-141/+284
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: Teach SCEV to match patterns like ``` br %cond, label %left, label %right left: br label %merge right: br label %merge merge: V = phi [ %x, %left ], [ %y, %right ] ``` as "select %cond, %x, %y". Before this SCEV would match PHI nodes exclusively to add recurrences. This addresses PR25005. Reviewers: joker.eph, joker-eph, atrick Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D13378 llvm-svn: 249211
* inariant.group handling in GVNPiotr Padlewski2015-10-027-33/+105
| | | | | | | | | | | | The most important part required to make clang devirtualization works ( ͡°͜ʖ ͡°). The code is able to find non local dependencies, but unfortunatelly because the caller can only handle local dependencies, I had to add some restrictions to look for dependencies only in the same BB. http://reviews.llvm.org/D12992 llvm-svn: 249196
* [libFuzzer] remove experimental flag and functionalityKostya Serebryany2015-10-025-38/+3
| | | | llvm-svn: 249194
* [WebAssembly] Fix CFG stackification of nested loops.Dan Gohman2015-10-021-4/+15
| | | | llvm-svn: 249187
* [WebAssembly] Support calls marked as "tail", fastcc, and coldcc.Dan Gohman2015-10-021-4/+14
| | | | llvm-svn: 249184
* Call the correct overload.Richard Trieu2015-10-021-2/+4
| | | | | | | Call the correct overload so a string literal does not get converted to a bool. Also fix the test case to match the names given. llvm-svn: 249183
* [libFuzzer] add a flag -max_total_timeKostya Serebryany2015-10-025-1/+12
| | | | llvm-svn: 249181
* [WebAssembly] Add a resize_memory intrinsic.Dan Gohman2015-10-021-0/+8
| | | | llvm-svn: 249178
* [SCEV] Refactor out a createNodeForSelectSanjoy Das2015-10-021-88/+100
| | | | | | | | | | | | | Summary: We will shortly re-use this for select-like br-phi pairs. Reviewers: atrick, joker-eph, joker.eph Subscribers: sanjoy, llvm-commits Differential Revision: http://reviews.llvm.org/D13377 llvm-svn: 249177
* [WebAssembly] Add a memory_size intrinsic.Dan Gohman2015-10-021-0/+8
| | | | llvm-svn: 249171
* AMDGPU/SI: Add verifier check for exec readsMatt Arsenault2015-10-022-2/+14
| | | | | | | Make sure we aren't accidentally not setting these in the instruction definitions. llvm-svn: 249170
* [SCEV] Try to prove predicates by splitting themSanjoy Das2015-10-021-3/+33
| | | | | | | | | | | | | | | | | | | | | Summary: This change teaches SCEV that to prove `A u< B` it is sufficient to prove each of these facts individually: - B >= 0 - A s< B - A >= 0 In practice, SCEV sometimes finds it easier to prove these facts individually than to prove `A u< B` as one atomic step. Reviewers: reames, atrick, nlewycky, hfinkel Subscribers: sanjoy, llvm-commits Differential Revision: http://reviews.llvm.org/D13042 llvm-svn: 249168
* Actually switch the arch when we see .arch. PR21695Roman Divacky2015-10-021-0/+5
| | | | llvm-svn: 249165
* ARM: diagnose invalid local fixups on Thumb1Tim Northover2015-10-022-20/+62
| | | | | | | | | We previously stopped producing Thumb2 relaxations when they weren't supported, but only diagnosed the case where an actual relocation was produced. We should also tell people if local symbols aren't going to work rather than silently overflowing. llvm-svn: 249164
* ARM: correctly align constant pool value on Thumb1 targets.Tim Northover2015-10-021-1/+1
| | | | | | | Since we're using tLDRpci to access it, the constant pool's address must be 0 (mod 4). llvm-svn: 249163
* [ARM] Typo. NFC.Chad Rosier2015-10-021-1/+1
| | | | llvm-svn: 249153
* Reapply r249121 : "[FastISel][x86] Teach how to select SSE2/AVX bitcasts ↵Andrea Di Biagio2015-10-021-0/+24
| | | | | | | | | | | | | | | | | | | | | | | between 128/256-bit vector types." This patch teaches FastIsel the following two things: 1) On SSE2, no instructions are needed for bitcasts between 128-bit vector types; 2) On AVX, no instructions are needed for bitcasts between 256-bit vector types. Example: %1 = bitcast <4 x i31> %V to <2 x i64> Before (-fast-isel -fast-isel-abort=1): FastIsel miss: %1 = bitcast <4 x i31> %V to <2 x i64> Now we don't fall back to SelectionDAG and we correctly fold that computation propagating the register associated to %V. Originally reviewed here: http://reviews.llvm.org/D13347 llvm-svn: 249147
* Revert: [FastISel][x86] Teach how to select SSE2/AVX bitcasts between ↵Andrea Di Biagio2015-10-021-24/+0
| | | | | | | | | 128/256-bit vector types. r249121 caused a Clang test failure (avx2-buitins.c). Revert r249121 while I keep investigating on the reason why that test failed. llvm-svn: 249124
* [mips][microMIPS] Fix an issue with selecting sqrt instruction in LLVM backendZoran Jovanovic2015-10-021-5/+2
| | | | | | Differential Revision: http://reviews.llvm.org/D13235 llvm-svn: 249123
* [FastISel][x86] Teach how to select SSE2/AVX bitcasts between 128/256-bit ↵Andrea Di Biagio2015-10-021-0/+24
| | | | | | | | | | | | | | | | | | | | | | | vector types. This patch teaches FastIsel the following two things: 1) On SSE2, no instructions are needed for bitcasts between 128-bit vector types; 2) On AVX, no instructions are needed for bitcasts between 256-bit vector types. Example: %1 = bitcast <4 x i31> %V to <2 x i64> Before (-fast-isel -fast-isel-abort=1): FastIsel miss: %1 = bitcast <4 x i31> %V to <2 x i64> Now we don't fall back to SelectionDAG and we correctly fold that computation propagating the register associated to %V. Differential Revision: http://reviews.llvm.org/D13347 llvm-svn: 249121
* [LibFuzzer] test_single_input option to run a single test case.Ivan Krasin2015-10-015-1/+13
| | | | | | | | | | -test_single_input flag specifies a file name with test data. Review URL: http://reviews.llvm.org/D13359 Patch by Mike Aizatsky! llvm-svn: 249096
* [SimplifyLibCalls] Fix instruction misplacement in string/memory libcall ↵Bruno Cardoso Lopes2015-10-011-2/+6
| | | | | | | | | | | | | | | | | | optimization When trying to optimize fortified library functions use the right location to insert new instructions in order to preserve correct def-use order. This fixes an issue where a misplaced instruction definition would happen to be *after* one of its use after a RAUW, forming invalid IR. This behavior was introduced by r227250. Differential Revision: http://reviews.llvm.org/D13301 rdar://problem/22802369 llvm-svn: 249092
* AMDGPU: Fix unused variable warning in release buildMatt Arsenault2015-10-011-2/+2
| | | | llvm-svn: 249091
* AMDGPU: Move SIFixSGPRLiveRanges to be a regalloc passMatt Arsenault2015-10-012-33/+40
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Replace LiveInterval usage with LiveVariables. LiveIntervals computes far more information than is needed for this pass which just needs to find if an SGPR is live out of the defining block. LiveIntervals are not usually available that early, requiring computing them twice which is very expensive. The extra run of LiveIntervals/LiveVariables/SlotIndexes was costing in total about 5% of compile time. Continuing to use LiveIntervals is problematic. It seems there is an option (early-live-intervals) to run the analysis about where it should go to avoid recomputing LiveVariables, but it seems to be completely broken with subreg liveness enabled. There are also problems from trying to recompute LiveIntervals since this seems to undo LiveVariables and clearing kill flags, causing TwoAddressInstructions to make bad decisions. Insert the pass right after live variables and preserve it. The tricky case to worry about might be phis since LiveVariables doesn't count a register as live out if in the successor block it is only used in a phi, but I don't think this is a concern right now because SIFixSGPRCopies replaces SGPR phis. llvm-svn: 249087
* Fix relocation used for GOT references in non-PIC mode. Fix relocationsJoerg Sonnenberger2015-10-011-28/+33
| | | | | | | | for "set" pseudo op in PIC mode. Differential Revision: http://reviews.llvm.org/D13173 llvm-svn: 249086
* AMDGPU: Merge if and switchMatt Arsenault2015-10-011-14/+17
| | | | llvm-svn: 249082
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