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* [NVPTX] Fixed lowering of unaligned loads/stores of f16 scalars and vectors.Artem Belevich2017-03-071-11/+31
| | | | | | Differential Revision: https://reviews.llvm.org/D30672 llvm-svn: 297198
* SjLjEHPrepare: Fix the pass for swifterror argumentsArnold Schwaighofer2017-03-071-0/+22
| | | | | | | | | | | We cannot leave the identity copies 'select true, arg, undef' that this pass inserts for arguments to simplify handling of values on swifterror arguments. swifterror arguments have restrictions on their uses. rdar://30839288 llvm-svn: 297197
* Fix C2712 build error on WindowsKonstantin Zhuravlyov2017-03-071-6/+12
| | | | | | | | Move the __try/__except block outside of the set_thread_name function to avoid a conflict with object unwinding due to the use of the llvm::Storage. Differential Revision: https://reviews.llvm.org/D30707 llvm-svn: 297192
* [AArch64] Vulcan is now ThunderXT99Joel Jones2017-03-075-193/+203
| | | | | | | | | | | | | | | | | Broadcom Vulcan is now Cavium ThunderX2T99. LLVM Bugzilla: http://bugs.llvm.org/show_bug.cgi?id=32113 Minor fixes for the alignments of loops and functions for ThunderX T81/T83/T88 (better performance). Patch was tested with SpecCPU2006. Patch by Stefan Teleman Differential Revision: https://reviews.llvm.org/D30510 llvm-svn: 297190
* Revert r297177: Change LLT constructor string into an LLT-based object ...Daniel Sanders2017-03-077-77/+61
| | | | | | | | | | More module problems. This time it only showed up in the stage 2 compile of clang-x86_64-linux-selfhost-modules-2 but not the stage 1 compile. Somehow, this change causes the build to need Attributes.gen before it's been generated. llvm-svn: 297188
* [JumpThread] Simplify CmpInst-as-Condition branch-folding a bit.Xin Tong2017-03-071-4/+11
| | | | | | | | | | | | | | Summary: Simplify CmpInst-as-Condition branch-folding a bit. Reviewers: sanjoy, efriedma Reviewed By: efriedma Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D30429 llvm-svn: 297186
* [ObjectYAML] Add support for DWARF5 Unit headerChris Bieneman2017-03-072-2/+11
| | | | | | In DWARF5 the Unit header added a new field, UnitType, and swapped the order of the address size and abbreviation offset fields. llvm-svn: 297183
* [LV] Consider users that are memory accesses in uniforms expansion stepMatthew Simpson2017-03-071-1/+3
| | | | | | | | | | | When expanding the set of uniform instructions beyond the seed instructions (e.g., consecutive pointers), we mark a new instruction uniform if all its loop-varying users are uniform. We should also allow users that are consecutive or interleaved memory accesses. This fixes cases where we have an instruction that is used as the pointer operand of a consecutive access but also used by a non-memory instruction that later becomes uniform as part of the expansion. llvm-svn: 297179
* [X86] Add option to specify preferable loop alignmentSanjoy Das2017-03-071-1/+9
| | | | | | | | | | | | | | | | | | | | | Summary: Loop alignment can cause a significant change of the perfromance for short loops. To be able to evaluate the impact of loop alignment this change introduces the new option x86-experimental-pref-loop-alignment. The alignment will be 2^Value bytes, the default value is 4. Patch by Serguei Katkov! Reviewers: craig.topper Reviewed By: craig.topper Subscribers: sanjoy, llvm-commits Differential Revision: https://reviews.llvm.org/D30391 llvm-svn: 297178
* [globalisel] Change LLT constructor string into an LLT-based object that ↵Daniel Sanders2017-03-077-61/+77
| | | | | | | | | | | | | | | | | | knows how to generate it. Summary: This will allow future patches to inspect the details of the LLT. The implementation is now split between the Support and CodeGen libraries to allow TableGen to use this class without introducing layering concerns. Thanks to Ahmed Bougacha for finding a reasonable way to avoid the layering issue and providing the version of this patch without that problem. Reviewers: t.p.northover, qcolombet, rovka, aditya_nandakumar, ab, javed.absar Subscribers: arsenm, nhaehnle, mgorny, dberris, llvm-commits, kristof.beyls Differential Revision: https://reviews.llvm.org/D30046 llvm-svn: 297177
* [GlobalISel] Translate floating-point negationVolkan Keles2017-03-071-0/+12
| | | | | | | | | | | | Reviewers: qcolombet, javed.absar, aditya_nandakumar, dsanders, t.p.northover, ab Reviewed By: qcolombet Subscribers: dberris, rovka, llvm-commits, kristof.beyls Differential Revision: https://reviews.llvm.org/D30671 llvm-svn: 297171
* Rephrase condition for better readability. NFCAdrian Prantl2017-03-071-1/+1
| | | | llvm-svn: 297168
* [fs] Make sure to check S_ISLNK() in fillStatus.Zachary Turner2017-03-071-0/+2
| | | | llvm-svn: 297167
* revert r297155 because there's a clang test that depends on InstCombine:Sanjay Patel2017-03-071-20/+0
| | | | | | tools/clang/test/CodeGen/zvector.c llvm-svn: 297166
* Revert "Strip debug info when inlining into a nodebug function."Adrian Prantl2017-03-071-30/+12
| | | | | | | | | | This reverts commit r296488. As noted by David Blaikie on llvm-commits, I overlooked the case of a debug function being inlined into a nodebug function being inlined into a debug function. llvm-svn: 297163
* Relax the conflicting function arg verifier to allow for inlined debugAdrian Prantl2017-03-071-0/+10
| | | | | | info in nodebug functions. llvm-svn: 297161
* Verfier: Move the reset of DebugFnArgs closer to other similar operations.Adrian Prantl2017-03-071-2/+1
| | | | | | NFC llvm-svn: 297160
* Revert r297132, it caused PR32171Nico Weber2017-03-071-45/+3
| | | | llvm-svn: 297159
* [InstCombine] shrink truncated splat shuffleSanjay Patel2017-03-071-0/+20
| | | | | | | | | | | | | This is one part of solving a recent bug report: http://lists.llvm.org/pipermail/llvm-dev/2017-February/110293.html This keeps with our general approach: changing arbitrary shuffles is off-limts, but changing splat is ok. The transform is very similar to the existing shrinkBitwiseLogic() canonicalization. Differential Revision: https://reviews.llvm.org/D30123 llvm-svn: 297155
* [Support] Add the option to not follow symlinks on stat.Zachary Turner2017-03-073-21/+12
| | | | llvm-svn: 297154
* [ARM] Correct handling of LSL #0 in an IT blockJohn Brawn2017-03-071-1/+1
| | | | | | | | | | | The check for LSL #0 in an IT block was checking if operand 4 was zero, but operand 4 is the condition code operand so it was actually checking for LSLEQ. Fix this by checking operand 3, which really is the immediate operand, and add some tests. Differential Revision: https://reviews.llvm.org/D30692 llvm-svn: 297142
* [Hexagon] Do not insert instructions before PHI nodesKrzysztof Parzyszek2017-03-071-1/+3
| | | | llvm-svn: 297141
* [ARM] Reapply r296865 "[ARM] fpscr read/write intrinsics not aware of each ↵Ranjeet Singh2017-03-071-3/+4
| | | | | | | | | | | | | | | | | | | | other"" The original patch r296865 was reverted as it broke the chromium builds for Android https://bugs.llvm.org/show_bug.cgi?id=32134, this patch reapplies r296865 with a fix to make sure it doesn't cause the build regression. The problem was that intrinsic selection on int_arm_get_fpscr was failing in ISel this was because the code to manually select this intrinsic still thought it was the version with no side-effects (INTRINSIC_WO_CHAIN) which is wrong as it doesn't semantically match the definition in the tablegen code which says it does have side-effects, I've fixed this by updating the intrinsic type to INTRINSIC_W_CHAIN (has side-effects). I've also added a test for this based on Hans original reproducer. Differential Revision: https://reviews.llvm.org/D30645 llvm-svn: 297137
* [SystemZ] Add check VT.isSimple() in canTreateAsByteVector()Jonas Paulsson2017-03-071-1/+1
| | | | | | | | Since BB-vectorizer can produce vectors of for example 3 elements, this check is needed. Review: Ulrich Weigand llvm-svn: 297136
* In Thumb1, materialize a move between low registers as a `movs`, if CPSR ↵Artyom Skrobov2017-03-071-5/+11
| | | | | | | | | | | | | | | | isn't live. Summary: Previously, it had always been materialized as a push/pop sequence. Reviewers: labrinea, jroelofs Reviewed By: jroelofs Subscribers: llvm-commits, rengolin Differential Revision: https://reviews.llvm.org/D30648 llvm-svn: 297134
* [LoopRotate] Update dbg.value intrinsicsSam Parker2017-03-071-3/+45
| | | | | | | | Propagate debug info through the newly inserted PHI nodes. Differential Revision: https://reviews.llvm.org/D30190 llvm-svn: 297132
* [X86][AVX512] Adding new LLVM TableGen backend which generates the EVEX2VEX ↵Ayman Musa2017-03-073-1193/+8
| | | | | | | | | | | | compressing tables. X86EvexToVex machine instruction pass compresses EVEX encoded instructions by replacing them with their identical VEX encoded instructions when possible. It uses manually supported 2 large tables that map the EVEX instructions to their VEX ideticals. This TableGen backend replaces the tables by automatically generating them. Differential Revision: https://reviews.llvm.org/D30451 llvm-svn: 297127
* [X86][AVX512] Add missing entries to EVEX2VEX tablesAyman Musa2017-03-071-28/+61
| | | | | | | | evex2vex pass defines 2 tables which maps EVEX instructions to their VEX identical when possible. Adding all missing entries. Differential Revision: https://reviews.llvm.org/D30501 llvm-svn: 297126
* Revert "[PowerPC][ELFv2ABI] Allocate parameter area on-demand to reduce ↵Tim Shen2017-03-071-43/+5
| | | | | | | | | | | stack frame size" This reverts commit r296771. We found some wide spread test failures internally. I'm working on a testcase. Politely revert the patch in the mean time. :) llvm-svn: 297124
* [LoopUnrolling] Fix loop size check for peelingSanjoy Das2017-03-071-1/+3
| | | | | | | | | | | | | | | | | | Summary: We should check if loop size allows us to peel at least one iteration before we do so. Patch by Max Kazantsev! Reviewers: sanjoy, mkuper, efriedma Reviewed By: mkuper Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D30632 llvm-svn: 297122
* [APInt] Add rvalue reference support to and, or, xor operations to allow ↵Craig Topper2017-03-071-25/+0
| | | | | | | | | | | | | | | | their memory allocation to be reused when possible This extends an earlier change that did similar for add and sub operations. With this first patch we lose the fastpath for the single word case as operator&= and friends don't support it. This can be added there if we think that's important. I had to change some functions in the APInt class since the operator overloads were moved out of the class and can't be used inside the class now. The getBitsSet change collides with another outstanding patch to implement it with setBits. But I didn't want to make this patch dependent on that series. I've also removed the Or, And, Xor functions which were rarely or never used. I already commited two changes to remove the only uses of Or that existed. Differential Revision: https://reviews.llvm.org/D30612 llvm-svn: 297121
* Revert "AMDGPU: Set MCAsmInfo::PointerSize"Konstantin Zhuravlyov2017-03-071-1/+0
| | | | | | | | It breaks line tables because the patch is not complete, working on a complete one at the moment This reverts commit r294031. llvm-svn: 297118
* Use LLVM for all stat-related functionality.Zachary Turner2017-03-071-0/+7
| | | | | | | | | | This deletes LLDB's FileType enumeration and replaces all users, and all calls to functions that check whether a file exists etc with corresponding calls to LLVM. Differential Revision: https://reviews.llvm.org/D30624 llvm-svn: 297116
* [APInt] Add setLowBits/setHighBits methods to APInt.Craig Topper2017-03-071-29/+23
| | | | | | | | | | | | | | | | | | | | | Summary: There are quite a few places in the code base that do something like the following to set the high or low bits in an APInt. KnownZero |= APInt::getHighBitsSet(BitWidth, BitWidth - 1); For BitWidths larger than 64 this creates a short lived APInt with malloced storage. I think it might even call malloc twice. Its better to just provide methods that can set the necessary bits without the temporary APInt. I'll update usages that benefit in a separate patch. Reviewers: majnemer, MatzeB, davide, RKSimon, hans Reviewed By: hans Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D30525 llvm-svn: 297111
* Un-XFAIL Fuzzer/test/dump_coverage.test. This now passes on Darwin (after ↵Kuba Mracek2017-03-071-2/+0
| | | | | | r297094). llvm-svn: 297110
* [SLP] Revert r296863 due to miscompiles.Michael Kuperstein2017-03-062-103/+80
| | | | | | Details and reproducer are on the email thread for r296863. llvm-svn: 297103
* GlobalISel: restrict G_EXTRACT instruction to just one operand.Tim Northover2017-03-0610-76/+73
| | | | | | | A bit more painful than G_INSERT because it was more widely used, but this should simplify the handling of extract operations in most locations. llvm-svn: 297100
* [libfuzzer] do not use xargs for shell expansionMike Aizatsky2017-03-061-1/+1
| | | | | | | | | Summary: After https://reviews.llvm.org/rL296904 xargs shouldn't be necesssary. Differential Revision: https://reviews.llvm.org/D30371 llvm-svn: 297094
* [InstCombine] use dyn_cast instead of isa+cast; NFCISanjay Patel2017-03-061-15/+12
| | | | llvm-svn: 297092
* [ObjectYAML] Support for DW_FORM_implicit_const DWARF5 formChris Bieneman2017-03-062-0/+4
| | | | | | | | This patch adds support to the DWARF YAML reader and writer for the new DWARF5 abbreviation form, DW_FORM_implicit_const. The attribute was added in r291599. llvm-svn: 297091
* [DAG] refactor related div/rem folds; NFCISanjay Patel2017-03-061-28/+32
| | | | | | | | | | | This is known incomplete and not called in the right order relative to other folds, but that's the current behavior. I'm just trying to clean this up before making actual functional changes to make the patch smaller. The logic here should mimic the IR equivalents that are in InstSimplify's simplifyDivRem(). llvm-svn: 297086
* [DWARFv5] Update definitions to match published spec.Paul Robinson2017-03-064-9/+50
| | | | | | | | | | | | | Some late additions to DWARF v5 were not in Dwarf.def; also one form was redefined. Add the new cases to relevant switches in different parts of LLVM. Replace DW_FORM_ref_sup with DW_FORM_ref_sup[4,8]. I did not add support for DW_FORM_strx3/addrx3 other that defining the constants. We don't have any infrastructure to support these. Differential Revision: http://reviews.llvm.org/D30664 llvm-svn: 297085
* [Outliner] Fixed Asan bot failure in r296418Jessica Paquette2017-03-066-0/+1506
| | | | | | | | Fixed the asan bot failure which led to the last commit of the outliner being reverted. The change is in lib/CodeGen/MachineOutliner.cpp in the SuffixTree's constructor. LeafVector is no longer initialized using reserve but just a standard constructor. llvm-svn: 297081
* [AArch64][Redundant Copy Elim] Add support for CMN and shifted imm.Chad Rosier2017-03-061-6/+13
| | | | | | | | | | This patch extends the current functionality of the AArch64 redundant copy elimination pass to handle CMN instructions as well as a shifted immediates. Differential Revision: https://reviews.llvm.org/D30576. llvm-svn: 297078
* Disable gvn-hoist (PR32153)Hans Wennborg2017-03-061-2/+2
| | | | llvm-svn: 297075
* Verifier: Change Assert to AssertDI.Adrian Prantl2017-03-061-3/+3
| | | | | | | This error can be recovered from by stripping debug info. This is NFC for +asserts builds. llvm-svn: 297072
* [ObjectYAML] NFC. Refactor DWARFYAML CompileUnit dump codeChris Bieneman2017-03-064-122/+324
| | | | | | | | | | | | Summary: This patch refactors the DWARFYAML code for dumping compile units to use a visitor pattern. Using this design will, in the future, enable the DWARF YAML code to perform analysis and mutations of the DWARF DIEs. An example of such mutations would be calculating the length of a compile unit and updating the CU's Length field before writing the DIE. This support will make it easier to craft or modify DWARF tests by hand. Reviewers: lhames Subscribers: mgorny, fhahn, jgosnell, aprantl, llvm-commits Differential Revision: https://reviews.llvm.org/D30357 llvm-svn: 297067
* AMDGPU/R600: Fix ALU clause markers use detectionJan Vesely2017-03-061-2/+5
| | | | | | | | also exit early on kill instead of redefinition. Differential Revision: https://reviews.llvm.org/D30230 llvm-svn: 297060
* [IfConversion] Only renormalize probabilities if branches are analyzableKrzysztof Parzyszek2017-03-061-2/+4
| | | | | | | | | | | If a block has non-analyzable branches, the listed successors don't need to add up to one. For example, if a block has a conditional tail call, that tail call will not have a corresponding successor in the successor list, but will still be a possible branch. Differential Revision: https://reviews.llvm.org/D30556 llvm-svn: 297054
* [InstSimplify] refactor related div/rem folds; NFCISanjay Patel2017-03-061-47/+37
| | | | llvm-svn: 297052
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