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author | Artem Belevich <tra@google.com> | 2017-03-07 20:33:38 +0000 |
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committer | Artem Belevich <tra@google.com> | 2017-03-07 20:33:38 +0000 |
commit | 2524a22562a2314dcdcd44cc3ef24fd677b46c4f (patch) | |
tree | eaa9991688192f7c7e3a9bfe93ed23159d309c48 /llvm/lib | |
parent | 69e74b48f2f2afee9186f4dcda0ab84167f381a4 (diff) | |
download | bcm5719-llvm-2524a22562a2314dcdcd44cc3ef24fd677b46c4f.tar.gz bcm5719-llvm-2524a22562a2314dcdcd44cc3ef24fd677b46c4f.zip |
[NVPTX] Fixed lowering of unaligned loads/stores of f16 scalars and vectors.
Differential Revision: https://reviews.llvm.org/D30672
llvm-svn: 297198
Diffstat (limited to 'llvm/lib')
-rw-r--r-- | llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp | 42 |
1 files changed, 31 insertions, 11 deletions
diff --git a/llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp b/llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp index c2877c34f63..8b3e49abc82 100644 --- a/llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp +++ b/llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp @@ -2071,8 +2071,21 @@ SDValue NVPTXTargetLowering::LowerSelect(SDValue Op, SelectionDAG &DAG) const { SDValue NVPTXTargetLowering::LowerLOAD(SDValue Op, SelectionDAG &DAG) const { if (Op.getValueType() == MVT::i1) return LowerLOADi1(Op, DAG); - else - return SDValue(); + + // v2f16 is legal, so we can't rely on legalizer to handle unaligned + // loads and have to handle it here. + if (Op.getValueType() == MVT::v2f16) { + LoadSDNode *Load = cast<LoadSDNode>(Op); + EVT MemVT = Load->getMemoryVT(); + if (!allowsMemoryAccess(*DAG.getContext(), DAG.getDataLayout(), MemVT, + Load->getAddressSpace(), Load->getAlignment())) { + SDValue Ops[2]; + std::tie(Ops[0], Ops[1]) = expandUnalignedLoad(Load, DAG); + return DAG.getMergeValues(Ops, SDLoc(Op)); + } + } + + return SDValue(); } // v = ld i1* addr @@ -2098,16 +2111,23 @@ SDValue NVPTXTargetLowering::LowerLOADi1(SDValue Op, SelectionDAG &DAG) const { } SDValue NVPTXTargetLowering::LowerSTORE(SDValue Op, SelectionDAG &DAG) const { - EVT ValVT = Op.getOperand(1).getValueType(); - switch (ValVT.getSimpleVT().SimpleTy) { - case MVT::i1: + StoreSDNode *Store = cast<StoreSDNode>(Op); + EVT VT = Store->getMemoryVT(); + + if (VT == MVT::i1) return LowerSTOREi1(Op, DAG); - default: - if (ValVT.isVector()) - return LowerSTOREVector(Op, DAG); - else - return SDValue(); - } + + // v2f16 is legal, so we can't rely on legalizer to handle unaligned + // stores and have to handle it here. + if (VT == MVT::v2f16 && + !allowsMemoryAccess(*DAG.getContext(), DAG.getDataLayout(), VT, + Store->getAddressSpace(), Store->getAlignment())) + return expandUnalignedStore(Store, DAG); + + if (VT.isVector()) + return LowerSTOREVector(Op, DAG); + + return SDValue(); } SDValue |