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* [CGP] Avoid segmentation fault when doing PHI node simplificationsBjorn Pettersson2018-03-201-61/+71
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: Made PHI node simplifiations more robust in several ways: - Minor refactoring to let the SimplificationTracker own the sets with new PHI/Select nodes that are introduced. This is maybe not mapping to the original intention with the SimplificationTracker, but IMHO it encapsulates the logic behind those sets a little bit better. - MatchPhiNode can sometimes populate the Matched set with several entries, where it maps one PHI node to different candidates for replacement. The Matched set is changed into a SmallSetVector to make sure we get a deterministic iteration when doing the replacements. - As described above we may get several different replacements for a single PHI node. The loop in MatchPhiSet that is doing the replacements could end up calling eraseFromParent several times for the same PHI node, resulting in segmentation faults. This problem was supposed to be fixed in rL327250, but due to the non-determinism(?) it only appeared to be fixed (I still got crashes sometime when turning on/off -print-after-all etc to get different iteration order in the DenseSets). With this patch we follow the deterministic ordering in the Matched set when replacing the PHI nodes. If we find a new replacement for an already replaced PHI node we replace the new replacement by the old replacement instead. This is quite similar to what happened in the rl327250 patch, but here we also recursively verify that the old replacement hasn't been replaced already. - It was really hard to track down the fault described above (segementation fault due to doing eraseFromParent multiple times for the same instruction). The fault was intermittent and small changes in the code, or simply turning on -print-after-all etc could make the problem go away. This was basically due to the iteration over PhiNodesToMatch in MatchPhiSet no being deterministic. Therefore I've changed the data structure for the SimplificationTracker::AllPhiNodes into an SmallSetVector. This gives a deterministic behavior. Reviewers: skatkov, john.brawn Reviewed By: skatkov Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D44571 llvm-svn: 327961
* [LV] Let recordVectorLoopValueForInductionCast to check if IV was created ↵Andrei Elovikov2018-03-201-15/+37
| | | | | | | | | | | | | | | | | | | | | | from the cast. Summary: It turned out to be error-prone to expect the callers to handle that - better to leave the decision to this routine and make the required data to be explicitly passed to the function. This handles the case that was missed in the r322473 and fixes the assert mentioned in PR36524. Reviewers: dorit, mssimpso, Ayal, dcaballe Reviewed By: dcaballe Subscribers: Ka-Ka, hiraditya, dneilson, hsaito, llvm-commits Differential Revision: https://reviews.llvm.org/D43812 llvm-svn: 327960
* [X86] Properly implement the calling convention for f80 for mingw/x86_64Martin Storsjo2018-03-201-7/+13
| | | | | | | | | | | | | | | | In these cases, both parameters and return values are passed as a pointer to a stack allocation. MSVC doesn't use the f80 data type at all, while it is used for long doubles on mingw. Normally, this part of the calling convention is handled within clang, but for intrinsics that are lowered to libcalls, it may need to be handled within llvm as well. Differential Revision: https://reviews.llvm.org/D44592 llvm-svn: 327957
* [ORC] Don't fully qualify explicit destructor call -- it confuses some ↵Lang Hames2018-03-201-4/+2
| | | | | | | | | compilers. This should fix the builder failure at http://lab.llvm.org:8011/builders/lld-x86_64-darwin13/builds/19224 llvm-svn: 327955
* [X86] Rename MOVSX32_NOREXrr8 to MOVSX32rr8_NOREX so that the scheduler ↵Craig Topper2018-03-204-15/+15
| | | | | | | | model regular expressions will pick it up with the regular version. Do the same for MOVSX32_NOREXrm8, MOVZX32_NOREXrr8, and MOVZX32_NOREXrm8 llvm-svn: 327948
* [X86] Fix the SchedRW for memory forms of CMP and TEST.Craig Topper2018-03-201-18/+21
| | | | | | | | They were incorrectly marked as RMW operations. Some of the CMP instrucions worked, but the ones that use a similar encoding as RMW form of ADD ended up marked as RMW. TEST used the same tablegen class as some of the CMPs. llvm-svn: 327947
* [ORC] Rename SymbolSource to MaterializationUnit, and make the materializationLang Hames2018-03-201-111/+167
| | | | | | | | | | | | | | | | | | | operation all-or-nothing, rather than allowing materialization on a per-symbol basis. This addresses a shortcoming of per-symbol materialization: If a MaterializationUnit (/SymbolSource) wants to materialize more symbols than requested (which is likely: most materializers will want to materialize whole modules) then it needs a way to notify the symbol table about the extra symbols being materialized. This process (checking what has been requested against what is being provided and notifying the symbol table about the difference) has to be repeated at every level of the JIT stack. Making materialization all-or-nothing eliminates this issue, simplifying both materializer implementations and the symbol table (VSO class) API. The cost is that per-symbol materialization (e.g. for individual symbols in a module) now requires multiple MaterializationUnits. llvm-svn: 327946
* [X86] Add TEST16mi/TEST32mi/TEST64mi32 to the ↵Craig Topper2018-03-205-6/+6
| | | | | | | | Sandybridge/Haswell/Broadwell/Skylake scheduler models. Move it from a load+store group on SNB to a load only group, the same group as CMP. llvm-svn: 327944
* [X86] Add ROR/ROL/SHR/SAR by 1 instructions to the Sandy Bridge scheduler model.Craig Topper2018-03-201-0/+8
| | | | | | I assume these match the generic immediate version like they do in the other models. llvm-svn: 327943
* [ShrinkWrap] Take into account landing padQuentin Colombet2018-03-201-0/+16
| | | | | | | | | | | | | When scanning the function for CSRs uses and defs, also check if the basic block are landing pads. Consider that landing pads needs the CSRs to be properly set. That way we force the prologue/epilogue to always be pushed out of the problematic "throw" region. The "throw" region is problematic because the jumps are not properly modeled. Fixes PR36513 llvm-svn: 327942
* [RISCV] Preserve stack space for outgoing arguments when the function ↵Shiva Chen2018-03-202-18/+38
| | | | | | | | | | | | | | | | | | | | | | | | | | contain variable size objects E.g. bar (int x) { char p[x]; push outgoing variables for foo. call foo } We need to generate stack adjustment instructions for outgoing arguments by eliminateCallFramePseudoInstr when the function contains variable size objects to avoid outgoing variables corrupt the variable size object. Default hasReservedCallFrame will return !hasFP(). We don't want to generate extra sp adjustment instructions when hasFP() return true, So We override hasReservedCallFrame as !hasVarSizedObjects(). Differential Revision: https://reviews.llvm.org/D43752 llvm-svn: 327938
* [X86] Fix the SNB scheduler for BLENDVB.Craig Topper2018-03-201-1/+2
| | | | | | PBLENDVBrr0 was with the memory version of VBLENDVB and PBLENDVBrm0 was missing. llvm-svn: 327937
* Object: Fix handling of @@@ in .symver directiveVitaly Buka2018-03-201-10/+37
| | | | | | | | | | | | | | | | | Summary: name@@@nodename is going to be replaced with name@@nodename if symbols is defined in the assembled file, or name@nodename if undefined. https://sourceware.org/binutils/docs/as/Symver.html Fixes PR36623 Reviewers: pcc, espindola Subscribers: mehdi_amini, hiraditya Differential Revision: https://reviews.llvm.org/D44274 llvm-svn: 327930
* Object: Move attribute calculation into RecordStreamer. NFCVitaly Buka2018-03-203-97/+94
| | | | | | | | | | | | Summary: Preparation for D44274 Reviewers: pcc, espindola Subscribers: hiraditya Differential Revision: https://reviews.llvm.org/D44276 llvm-svn: 327928
* [SelectionDAG] Transfer DbgValues when integer operations are promotedAaron Smith2018-03-191-0/+2
| | | | | | | | | | | | | | | | | | | | | Summary: DbgValue nodes were not transferred when integer DAG nodes were promoted. For example, if an i32 add node was promoted to an i64 add node by DAGTypeLegalizer::PromoteIntegerResult(), its DbgValue node was not transferred to the new node. The simple fix is to update SetPromotedInteger() to transfer DbgValues. Add AArch64/dbg-value-i8.ll to test this change and fix ARM/debug-info-d16-reg.ll which had the wrong DILocalVariable nodes with arg numbers even though they are not for function parameters. Patch by Se Jong Oh! Reviewers: vsk, JDevlieghere, aprantl Reviewed By: JDevlieghere Subscribers: javed.absar, kristof.beyls, llvm-commits Tags: #debug-info Differential Revision: https://reviews.llvm.org/D44546 llvm-svn: 327919
* [MachineOutliner] AArch64: Emit CFI instructions when outlining callsJessica Paquette2018-03-191-0/+19
| | | | | | | | | | | When outlining calls, the outliner needs to update CFI to ensure that, say, exception handling works. This commit adds that functionality and adds a test just for call outlining. Call outlining stuff in machine-outliner.mir should be moved into machine-outliner-calls.mir in a later commit. llvm-svn: 327917
* [DAGCombiner] Fix type in comment. NFCCraig Topper2018-03-191-1/+1
| | | | llvm-svn: 327916
* [X86] Simplify the AVX512 code in LowerTruncate a little.Craig Topper2018-03-191-3/+2
| | | | | | We don't need to create an ISD::TRUNCATE node to return, we started with one and can return it. Also remove the call to getExtendInVec, the result is just going to be a getNode of that value passed in. llvm-svn: 327914
* [PDB] Add a method to get the full path of the source file for ↵Aaron Smith2018-03-191-15/+86
| | | | | | | | | | | | | | | | | PDBSymbolCompiland Summary: Redefine PDBSymbolCompiland::getSourceFileName() to return the filename (w/o directory) of the source file that is used to compile the compiland. This is because the result returned previously is ambiguous. It could be the filename, relative path or full path of the source file. Move the implementation of SymbolFilePDB::GetSourceFileNameForPDBCompiland() into a new method PDBSymbolCompiland::getSourceFileFullPath(). Reviewers: zturner, rnk, llvm-commits Reviewed By: zturner Differential Revision: https://reviews.llvm.org/D44458 llvm-svn: 327910
* [PDB] Add exclusive methods to derived symbol classAaron Smith2018-03-191-0/+15
| | | | | | | | | | | | Summary: This commit adds two methods to the PDBSymboFunc class used in parsing symbols. getLineNumbers() is used to determine a Function symbol's declaration and getCompilandId() is used to initialize the SymbolContext field sc.comp_unit. Reviewers: zturner, rnk, llvm-commits Reviewed By: zturner Differential Revision: https://reviews.llvm.org/D44457 llvm-svn: 327909
* Revert "Support embedding natvis files in PDBs."Zachary Turner2018-03-198-186/+32
| | | | | | | This is causing a test failure on a certain bot, so I'm removing this temporarily until we can figure out the source of the error. llvm-svn: 327903
* Remove an unused private variable.Zachary Turner2018-03-192-7/+4
| | | | llvm-svn: 327900
* [X86] Replace a couple calls to getExtendInVec with getNode and the ↵Craig Topper2018-03-191-5/+6
| | | | | | appropriate target independent EXTEND_VECTOR_INREG opcode. llvm-svn: 327899
* [DAG, X86] Revert r327197 "Revert r327170, r327171, r327172"Nirav Dave2018-03-197-278/+232
| | | | | | | Reland ISel cycle checking improvements after simplifying node id invariant traversal and correcting typo. llvm-svn: 327898
* [ARM, AArch64] Check the no-stack-arg-probe attribute for dynamic stack probesMartin Storsjo2018-03-192-0/+27
| | | | | | | | | | | | | This extends the use of this attribute on ARM and AArch64 from SVN r325900 (where it was only checked for fixed stack allocations on ARM/AArch64, but for all stack allocations on X86). This also adds a testcase for the existing use of disabling the fixed stack probe with the attribute on ARM and AArch64. Differential Revision: https://reviews.llvm.org/D44291 llvm-svn: 327897
* Support embedding natvis files in PDBs.Zachary Turner2018-03-196-25/+182
| | | | | | | | | | | | | | | | | | | | | | | | Natvis is a debug language supported by Visual Studio for specifying custom visualizers. The /NATVIS option is an undocumented link.exe flag which will take a .natvis file and "inject" it into the PDB. This way, you can ship the debug visualizers for a program along with the PDB, which is very useful for postmortem debugging. This is implemented by adding a new "named stream" to the PDB with a special name of /src/files/<natvis file name> and simply copying the contents of the xml into this file. Additionally, we need to emit a single stream named /src/headerblock which contains a hash table of embedded files to records describing them. This patch adds this functionality, including the /NATVIS option to lld-link. Differential Revision: https://reviews.llvm.org/D44328 llvm-svn: 327895
* Make ConstantDataArray::get constructor templated. Will support signed integers.Alina Sbirlea2018-03-191-34/+0
| | | | | | | | | | | | Summary: Make ConstantDataArray::get() constructors a single templated one. Reviewers: timshen, rsmith Subscribers: sanjoy, llvm-commits, jlebar Differential Revision: https://reviews.llvm.org/D44337 llvm-svn: 327894
* [Power9]Legalize and emit code for quad-precision copySign/abs/nabs/neg/sqrtLei Huang2018-03-191-5/+11
| | | | | | | | | | | | | | Legalize and emit code for quad-precision floating point operations: * xscpsgnqp * xsabsqp * xsnabsqp * xsnegqp * xssqrtqp Differential Revision: https://reviews.llvm.org/D44530 llvm-svn: 327889
* [X86] Add JMP16r and JMP32r to Sandybridge scheduler model.Craig Topper2018-03-191-1/+1
| | | | | | Fixes PR36010 llvm-svn: 327883
* [X86] Remove OUT32rr/OUT8rr/OUT32ri/OUT8ri from Sandybridge scheduler model.Craig Topper2018-03-191-4/+0
| | | | | | PR35590 was already filed for this information being wrong. It's probably better to default to WriteSystem behavior instead of using something completely wrong. llvm-svn: 327882
* [X86] Add JCXZ/JECXZ to Sandybridge/Haswell/Broadwell/Skylake scheduler models.Craig Topper2018-03-195-5/+5
| | | | | | | | JRCXZ was already present, but not the others. We never codegen this instruction so this doesn't affect much just trying to get them all into a single generated scheduler class in the output. llvm-svn: 327881
* [X86] Correct regular expression in Zen scheduler model that was excluding ↵Craig Topper2018-03-191-1/+1
| | | | | | | | JECXZ instruction. The regex was looking for JECXZ_32 or JECXZ_64, but their is just one instruction called JECXZ. They used to exist as separate instructions, but were merged over 3 years ago. llvm-svn: 327880
* [X86] Correct the SchedRW on (V)MOVAPSrr_REV and similar to match their non ↵Craig Topper2018-03-191-2/+2
| | | | | | _REV counterparts. llvm-svn: 327879
* [PowerPC][Power9]Legalize and emit code for quad-precision add/div/mul/subLei Huang2018-03-192-5/+27
| | | | | | | | | | | | | Legalize and emit code for quad-precision floating point operations: * xsaddqp * xssubqp * xsdivqp * xsmulqp Differential Revision: https://reviews.llvm.org/D44506 llvm-svn: 327878
* [PowerPC] Make AddrSpaceCast noopNemanja Ivanovic2018-03-191-0/+5
| | | | | | | | | | | PowerPC targets do not use address spaces. As a result, we can get selection failures with address space casts. This patch makes those casts noops. Patch by Valentin Churavy. Differential revision: https://reviews.llvm.org/D43781 llvm-svn: 327877
* [X86] Add the rest of the TEST with immediate instructions to the scheduler ↵Craig Topper2018-03-195-10/+10
| | | | | | models to match their 8-bit counterpart. llvm-svn: 327874
* [X86] Add MOV16ri*/MOV32ri*/MOV64ri* to scheduler models to match MOV8ri. ↵Craig Topper2018-03-196-9/+8
| | | | | | Correct SchedRW and itinerary for MOV32ri64. llvm-svn: 327872
* [X86] Remove sse41 specific code from lowering v16i8 multiplyCraig Topper2018-03-191-32/+16
| | | | | | With the SRAs removed from the SSE2 code in D44267, then there doesn't appear to be any advantage to the sse41 code. The punpcklbw instruction and pmovsx seem to have the same latency and throughput on most CPUs. And the SSE41 code requires moving the upper 64-bits into the lower 64-bit before the sign extend can be done. The unpckhbw in sse2 code can do better than that. llvm-svn: 327869
* [X86] Make the multiply and divide itineraries more consistent.Craig Topper2018-03-193-51/+76
| | | | | | | | | | Sometimes we used the same itinerary for MEM and REG forms, but that seems inconsistent with our usual usage. We also used the MUL8 itinerary for MULX32/64 which was also weird. The test changes are because we were using IIC_IMUL32_RR and IIC_IMUL64_RR instead of IIC_IMUL32_REG/IIC_IMUL64_REG for the 32 and 64 bit multiplies that produce double width result. llvm-svn: 327866
* Revert [MachineLICM] This reverts commit rL327856Zaara Syeda2018-03-196-136/+45
| | | | | | Failing build bots. Revert the commit now. llvm-svn: 327864
* [CodeGen] Avoid handling DBG_VALUE in the LivePhysRegs ↵Matt Davis2018-03-191-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | (addUses,removeDefs,stepForward) Summary: This patch prevents DBG_VALUE instructions from influencing LivePhysRegs::stepBackwards and stepForwards. In at least one case, specifically branch folding, the stepBackwards logic was having an influence on code generation. The result was that certain code compiled with '-g -O2' would differ from that compiled with '-O2' alone. It seems that the original logic, accounting for DBG_VALUE, was influencing the placement of an IMPLICIT_DEF which had a later impact on how blocks were processed in branch folding. Reviewers: kparzysz, MatzeB Reviewed By: kparzysz Subscribers: bjope, llvm-commits Tags: #debug-info Differential Revision: https://reviews.llvm.org/D43850 llvm-svn: 327862
* [demangler] Recopy the demangler from libcxxabi.Erik Pilkington2018-03-191-3943/+4521
| | | | | | | | | Some significant work has gone into libcxxabi's copy of this file: - Uses an AST to represent mangled names. - Support/bugfixes for many C++ features. - Uses LLVM coding style. llvm-svn: 327859
* [InstCombine] canonicalize fcmp+select to fabsSanjay Patel2018-03-191-1/+31
| | | | | | | | | | | | | | This is complicated by -0.0 and nan. This is based on the DAG patterns as shown in D44091. I'm hoping that we can just remove those DAG folds and always rely on IR canonicalization to handle the matching to fabs. We would still need to delete the broken code from DAGCombiner to fix PR36600: https://bugs.llvm.org/show_bug.cgi?id=36600 Differential Revision: https://reviews.llvm.org/D44550 llvm-svn: 327858
* [MachineLICM] Add functions to MachineLICM to hoist invariant storesZaara Syeda2018-03-196-45/+136
| | | | | | | | | | | | | | | | This patch adds functions to allow MachineLICM to hoist invariant stores. Currently, MachineLICM does not hoist any store instructions, however when storing the same value to a constant spot on the stack, the store instruction should be considered invariant and be hoisted. The function isInvariantStore iterates each operand of the store instruction and checks that each register operand satisfies isCallerPreservedPhysReg. The store may be fed by a copy, which is hoisted by isCopyFeedingInvariantStore. This patch also adds the PowerPC changes needed to consider the stack register as caller preserved. Differential Revision: https://reviews.llvm.org/D40196 llvm-svn: 327856
* [X86] Generalize schedule classes to support multiple stagesSimon Pilgrim2018-03-197-567/+308
| | | | | | | | | | | | Currently the WriteResPair style multi-classes take a single pipeline stage and latency, this patch generalizes this to make it easier to create complex schedules with ResourceCycles and NumMicroOps be overriden from their defaults. This has already been done for the Jaguar scheduler to remove a number of custom schedule classes and adding it to the other x86 targets will make it much tidier as we add additional classes in the future to try and replace so many custom cases. I've converted some instructions but a lot of the models need a bit of cleanup after the patch has been committed - memory latencies not being consistent, the class not actually being used when we could remove some/all customs, etc. I'd prefer to keep this as NFC as possible so later patches can be smaller and target specific. Differential Revision: https://reviews.llvm.org/D44612 llvm-svn: 327855
* [x86] put nops into the WriteNop class and customize for JaguarSanjay Patel2018-03-193-5/+7
| | | | | | | | | | | | 1. Given that we already have a classification bucket with 'nop' in the name, that's where 'nop' belongs. Right now, it's only used for prefix bytes and 'pause'. 2. Make the latency of this class '1' for Jaguar to tell the scheduler (and presumably llvm-mca) how to model the resource requirements better even though a nop has no dependencies. Differential Revision: https://reviews.llvm.org/D44608 llvm-svn: 327853
* Changed createTemporaryFile without FD to actually create a file.Ilya Biryukov2018-03-191-7/+32
| | | | | | | | | | | | | | | | | | | | | Summary: This commit changes semantics of createUniqueFile and createTemporaryFile variants that do not return file descriptors. Previously they only checked if files exist, therefore being subject to race conditions. Now they will create an empty file to avoid them. Functions that do not create a file are now called getPotentiallyUniqueTempFileName and getPotentiallyUniqueFileName. Reviewers: klimek, bkramer, krasimir, JDevlieghere, espindola Reviewed By: klimek Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D36827 llvm-svn: 327851
* TableGen: Explicitly forbid self-references to field membersNicolai Haehnle2018-03-192-4/+10
| | | | | | | | | | | | | | | | Summary: Otherwise, patterns like in the test case produce cryptic error messages about fields being resolved incompletely. Change-Id: I713c0191f00fe140ad698675803ab1f8823dc5bd Reviewers: arsenm, craig.topper, tra, MartinO Subscribers: wdng, llvm-commits Differential Revision: https://reviews.llvm.org/D44476 llvm-svn: 327850
* TableGen: Check the dynamic type of !cast<Rec>(string)Nicolai Haehnle2018-03-194-77/+100
| | | | | | | | | | | | | | | | | | | | | Summary: The docs already claim that this happens, but so far it hasn't. As a consequence, existing TableGen files get this wrong a lot, but luckily the fixes are all reasonably straightforward. To make this work with all the existing forms of self-references (since the true type of a record is only built up over time), the lookup of self-references in !cast is delayed until the final resolving step. Change-Id: If5923a72a252ba2fbc81a889d59775df0ef31164 Reviewers: arsenm, craig.topper, tra, MartinO Subscribers: wdng, javed.absar, llvm-commits Differential Revision: https://reviews.llvm.org/D44475 llvm-svn: 327849
* TableGen: Explicitly test some cases of self-references and !cast errorsNicolai Haehnle2018-03-192-7/+7
| | | | | | | | | | | | | | | | | | | | | | | Summary: These are cases of self-references that exist today in practice. Let's add tests for them to avoid regressions. The self-references in PPCInstrInfo.td can be expressed in a simpler way. Allowing this type of self-reference while at the same time consistently doing late-resolve even for self-references is problematic because there are references to fields that aren't in any class. Since there's no need for this type of self-reference anyway, let's just remove it. Change-Id: I914e0b3e1ae7adae33855fac409b536879bc3f62 Reviewers: arsenm, craig.topper, tra, MartinO Subscribers: nemanjai, wdng, kbarton, llvm-commits Differential Revision: https://reviews.llvm.org/D44474 llvm-svn: 327848
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