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| author | Craig Topper <craig.topper@intel.com> | 2018-03-19 19:00:35 +0000 |
|---|---|---|
| committer | Craig Topper <craig.topper@intel.com> | 2018-03-19 19:00:35 +0000 |
| commit | 5e65996facfdaca8d2411afdf1c4e4064dd59a83 (patch) | |
| tree | ad6251001727a13c0da6549c472fc434847d6ec5 /llvm/lib | |
| parent | b4c7873f8cb8131fdef833e6abfaac4261930f54 (diff) | |
| download | bcm5719-llvm-5e65996facfdaca8d2411afdf1c4e4064dd59a83.tar.gz bcm5719-llvm-5e65996facfdaca8d2411afdf1c4e4064dd59a83.zip | |
[X86] Remove OUT32rr/OUT8rr/OUT32ri/OUT8ri from Sandybridge scheduler model.
PR35590 was already filed for this information being wrong. It's probably better to default to WriteSystem behavior instead of using something completely wrong.
llvm-svn: 327882
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/Target/X86/X86SchedSandyBridge.td | 4 |
1 files changed, 0 insertions, 4 deletions
diff --git a/llvm/lib/Target/X86/X86SchedSandyBridge.td b/llvm/lib/Target/X86/X86SchedSandyBridge.td index d1b58a8106d..664b4d4f34d 100644 --- a/llvm/lib/Target/X86/X86SchedSandyBridge.td +++ b/llvm/lib/Target/X86/X86SchedSandyBridge.td @@ -1010,8 +1010,6 @@ def SBWriteResGroup25 : SchedWriteRes<[SBPort015]> { let ResourceCycles = [3]; } def: InstRW<[SBWriteResGroup25], (instregex "LEAVE64")>; -def: InstRW<[SBWriteResGroup25], (instregex "OUT32rr")>; -def: InstRW<[SBWriteResGroup25], (instregex "OUT8rr")>; def: InstRW<[SBWriteResGroup25], (instregex "XADD(8|16|32|64)rr")>; def SBWriteResGroup25_2 : SchedWriteRes<[SBPort5,SBPort05]> { @@ -1091,8 +1089,6 @@ def SBWriteResGroup29_2 : SchedWriteRes<[SBPort5,SBPort015]> { let NumMicroOps = 4; let ResourceCycles = [1,3]; } -def: InstRW<[SBWriteResGroup29_2], (instregex "OUT32ir")>; -def: InstRW<[SBWriteResGroup29_2], (instregex "OUT8ir")>; def: InstRW<[SBWriteResGroup29_2], (instregex "PAUSE")>; def SBWriteResGroup29_3 : SchedWriteRes<[SBPort05,SBPort015]> { |
