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* Make getOther ELF only.Rafael Espindola2015-06-261-3/+2
| | | | | | No other format has this field. llvm-svn: 240774
* Optimize the creation of mapping symbols.Rafael Espindola2015-06-262-19/+2
| | | | | | No need to create two symbols just to assign one to the other. llvm-svn: 240773
* [X86] Cleanup X86WindowsTargetObjectFile::getSectionForConstantDavid Majnemer2015-06-261-37/+25
| | | | | | No functionality changed, just keeping things clean. llvm-svn: 240762
* [InterleavedAccess] Fix failures "undefined type 'llvm::raw_ostream'" on ↵Hao Liu2015-06-261-0/+1
| | | | | | windows. llvm-svn: 240760
* [ARM] Lower interleaved memory accesses to vldN/vstN intrinsics.Hao Liu2015-06-265-0/+204
| | | | | | | | | | | | | | | | | | | | | | | | | | This patch also adds a function to calculate the cost of interleaved memory accesses. E.g. Lower an interleaved load: %wide.vec = load <8 x i32>, <8 x i32>* %ptr, align 4 %v0 = shuffle %wide.vec, undef, <0, 2, 4, 6> %v1 = shuffle %wide.vec, undef, <1, 3, 5, 7> into: %vld2 = { <4 x i32>, <4 x i32> } call llvm.arm.neon.vld2(%ptr, 4) %vec0 = extractelement { <4 x i32>, <4 x i32> } %vld2, i32 0 %vec1 = extractelement { <4 x i32>, <4 x i32> } %vld2, i32 1 E.g. Lower an interleaved store: %i.vec = shuffle <8 x i32> %v0, <8 x i32> %v1, <0, 4, 8, 1, 5, 9, 2, 6, 10, 3, 7, 11> store <12 x i32> %i.vec, <12 x i32>* %ptr, align 4 into: %sub.v0 = shuffle <8 x i32> %v0, <8 x i32> v1, <0, 1, 2, 3> %sub.v1 = shuffle <8 x i32> %v0, <8 x i32> v1, <4, 5, 6, 7> %sub.v2 = shuffle <8 x i32> %v0, <8 x i32> v1, <8, 9, 10, 11> call void llvm.arm.neon.vst3(%ptr, %sub.v0, %sub.v1, %sub.v2, 4) Differential Revision: http://reviews.llvm.org/D10533 llvm-svn: 240755
* [AArch64] Lower interleaved memory accesses to ldN/stN intrinsics. This ↵Hao Liu2015-06-265-0/+192
| | | | | | | | | | | | | | | | | | | | | | | | | | patch also adds a function to calculate the cost of interleaved memory accesses. E.g. Lower an interleaved load: %wide.vec = load <8 x i32>, <8 x i32>* %ptr %v0 = shuffle %wide.vec, undef, <0, 2, 4, 6> %v1 = shuffle %wide.vec, undef, <1, 3, 5, 7> into: %ld2 = { <4 x i32>, <4 x i32> } call llvm.aarch64.neon.ld2(%ptr) %vec0 = extractelement { <4 x i32>, <4 x i32> } %ld2, i32 0 %vec1 = extractelement { <4 x i32>, <4 x i32> } %ld2, i32 1 E.g. Lower an interleaved store: %i.vec = shuffle <8 x i32> %v0, <8 x i32> %v1, <0, 4, 8, 1, 5, 9, 2, 6, 10, 3, 7, 11> store <12 x i32> %i.vec, <12 x i32>* %ptr into: %sub.v0 = shuffle <8 x i32> %v0, <8 x i32> v1, <0, 1, 2, 3> %sub.v1 = shuffle <8 x i32> %v0, <8 x i32> v1, <4, 5, 6, 7> %sub.v2 = shuffle <8 x i32> %v0, <8 x i32> v1, <8, 9, 10, 11> call void llvm.aarch64.neon.st3(%sub.v0, %sub.v1, %sub.v2, %ptr) Differential Revision: http://reviews.llvm.org/D10533 llvm-svn: 240754
* [InterleavedAccess] Add a pass InterleavedAccess to identify interleaved ↵Hao Liu2015-06-262-0/+286
| | | | | | | | | | | | | | | | | | | memory accesses and transform into target specific intrinsics. E.g. An interleaved load (Factor = 2): %wide.vec = load <8 x i32>, <8 x i32>* %ptr %v0 = shuffle <8 x i32> %wide.vec, <8 x i32> undef, <0, 2, 4, 6> %v1 = shuffle <8 x i32> %wide.vec, <8 x i32> undef, <1, 3, 5, 7> It can be transformed into a ld2 intrinsic in AArch64 backend or a vld2 intrinsic in ARM backend. E.g. An interleaved store (Factor = 3): %i.vec = shuffle <8 x i32> %v0, <8 x i32> %v1, <0, 4, 8, 1, 5, 9, 2, 6, 10, 3, 7, 11> store <12 x i32> %i.vec, <12 x i32>* %ptr It can be transformed into a st3 intrinsic in AArch64 backend or a vst3 intrinsic in ARM backend. Differential Revision: http://reviews.llvm.org/D10533 llvm-svn: 240751
* Revert "X86: Reject register operands with obvious type mismatches."Matthias Braun2015-06-261-13/+0
| | | | | | | | Revert until http://llvm.org/PR23955 is investigated. This reverts commit r239309. llvm-svn: 240746
* [ASan] Use llvm::getDISubprogram() to get function entry debug location.Alexey Samsonov2015-06-261-7/+3
| | | | | | | | It can be more robust than copying debug info from first non-alloca instruction in the entry basic block. We use the same strategy in coverage instrumentation. llvm-svn: 240738
* AsmPrinter: Use an intrusively linked list for DIE::ChildrenDuncan P. N. Exon Smith2015-06-258-53/+47
| | | | | | | | | | | | | | Replace the `std::vector<>` for `DIE::Children` with an intrusively linked list. This is a strict memory improvement: it requires no auxiliary storage, and reduces `sizeof(DIE)` by one pointer. It also factors out the DIE-related malloc traffic. This drops llc memory usage from 735 MB down to 718 MB, or ~2.3%. (I'm looking at `llc` memory usage on `verify-uselistorder.lto.opt.bc`; see r236629 for details.) llvm-svn: 240736
* AsmPrinter: Convert DIE::Values to a linked listDuncan P. N. Exon Smith2015-06-257-59/+66
| | | | | | | | | | | | | | | | Change `DIE::Values` to a singly linked list, where each node is allocated on a `BumpPtrAllocator`. In order to support `push_back()`, the list is circular, and points at the tail element instead of the head. I abstracted the core list logic out to `IntrusiveBackList` so that it can be reused for `DIE::Children`, which also cares about `push_back()`. This drops llc memory usage from 799 MB down to 735 MB, about 8%. (I'm looking at `llc` memory usage on `verify-uselistorder.lto.opt.bc`; see r236629 for details.) llvm-svn: 240733
* PPCISelLowering.cpp: Appease PR23956. [-Wdocumentation]NAKAMURA Takumi2015-06-251-6/+6
| | | | llvm-svn: 240727
* [asan] Do not instrument special purpose LLVM sections.Anna Zaks2015-06-251-0/+2
| | | | | | | | | | | | | | Do not instrument globals that are placed in sections containing "__llvm" in their name. This fixes a bug in ASan / PGO interoperability. ASan interferes with LLVM's PGO, which places its globals into a special section, which is memcpy-ed by the linker as a whole. When those goals are instrumented, ASan's memcpy wrapper reports an issue. http://reviews.llvm.org/D10541 llvm-svn: 240723
* [asan] Don't run stack malloc on functions containing inline assembly.Anna Zaks2015-06-251-4/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | It makes LLVM run out of registers even on 64-bit platforms. For example, the following test case fails on darwin. clang -cc1 -O0 -triple x86_64-apple-macosx10.10.0 -emit-obj -fsanitize=address -mstackrealign -o ~/tmp/ex.o -x c ex.c error: inline assembly requires more registers than available void TestInlineAssembly(const unsigned char *S, unsigned int pS, unsigned char *D, unsigned int pD, unsigned int h) { unsigned int sr = 4, pDiffD = pD - 5; unsigned int pDiffS = (pS << 1) - 5; char flagSA = ((pS & 15) == 0), flagDA = ((pD & 15) == 0); asm volatile ( "mov %0, %%"PTR_REG("si")"\n" "mov %2, %%"PTR_REG("cx")"\n" "mov %1, %%"PTR_REG("di")"\n" "mov %8, %%"PTR_REG("ax")"\n" : : "m" (S), "m" (D), "m" (pS), "m" (pDiffS), "m" (pDiffD), "m" (sr), "m" (flagSA), "m" (flagDA), "m" (h) : "%"PTR_REG("si"), "%"PTR_REG("di"), "%"PTR_REG("ax"), "%"PTR_REG("cx"), "%"PTR_REG("dx"), "memory" ); } http://reviews.llvm.org/D10719 llvm-svn: 240722
* DAGCombiner: Use pop_back_val()Matt Arsenault2015-06-251-2/+1
| | | | llvm-svn: 240709
* Add an ELFSymbolRef type.Rafael Espindola2015-06-252-4/+4
| | | | | | | This allows user code to say Sym.getSize() instead of having to manually fetch the object. llvm-svn: 240708
* IAS: Use the root macro instanciation for locationFrederic Riss2015-06-251-2/+2
| | | | | | | | | | | | | | r224810 fixed the handling of macro debug locations in AsmParser. This patch fixes the logic to actually do what was intended: it uses the first macro of the macro stack instead of the last one. The updated testcase shows that the current scheme doesn't work when macro instanciations are nested and multiple files are used. Reviewers: compnerd Differential Revision: http://reviews.llvm.org/D10463 llvm-svn: 240705
* fix typos; NFCSanjay Patel2015-06-251-4/+4
| | | | llvm-svn: 240699
* Use foreach loop over constant operands. NFC.Pete Cooper2015-06-255-14/+9
| | | | | | | A number of places had explicit loops over Constant::operands(). Just use foreach loops where possible. llvm-svn: 240694
* [InstCombine] call SimplifyICmpInst with correct contextJingyue Wu2015-06-251-2/+4
| | | | | | | | | | | | | | | | | | | | | Summary: Fixes PR23809. Without passing the context to SimplifyICmpInst, we would use the assume to prove that the condition feeding the assume is trivially true (see isValidAssumeForContext in ValueTracking.cpp), causing the removal of the assume which may be useful for later optimizations. Test Plan: pr23800.ll Reviewers: hfinkel, majnemer Reviewed By: hfinkel Subscribers: henryhu, llvm-commits, wengxt, broune, meheff, eliben Differential Revision: http://reviews.llvm.org/D10695 llvm-svn: 240683
* Diagnose undefined temporary symbols.Rafael Espindola2015-06-251-0/+5
| | | | | | | | | | | | We already disallowed .global .Lfoo so this is reasonable. This is a small cherry pick from r240130. llvm-svn: 240681
* Rangify for loop in Inliner.cpp. NFC.Yaron Keren2015-06-251-8/+5
| | | | llvm-svn: 240678
* DAGCombiner: Remove redundant checkMatt Arsenault2015-06-251-1/+1
| | | | | | | MemIntrinsicSDNode is already a subclass of MemSDNode, so the MemSDNode check is sufficient. llvm-svn: 240672
* GVN: If a branch has two identical successors, we cannot declare either dead.Peter Collingbourne2015-06-251-0/+4
| | | | | | | | | This previously caused miscompilations as a result of phi nodes receiving undef incoming values from blocks dominated by such successors. Differential Revision: http://reviews.llvm.org/D10726 llvm-svn: 240670
* [PPC] Implement vmrgew and vmrgow instructionsKit Barton2015-06-253-2/+154
| | | | | | | | | This patch adds support for the vector merge even word and vector merge odd word instructions introduced in POWER8. Phabricator review: http://reviews.llvm.org/D10704 llvm-svn: 240650
* [AsmPrinter] Fix crash in handleIndirectSymViaGOTPCRelBruno Cardoso Lopes2015-06-251-2/+9
| | | | | | | | | | | Check for symbols in MCValue before using them. Bail out early in case they are null. This fixes PR23779. Differential Revision: http://reviews.llvm.org/D10712 rdar://problem/21532830 llvm-svn: 240649
* Use computeSymbolSizes in llvm-symbolize.Rafael Espindola2015-06-251-1/+4
| | | | llvm-svn: 240646
* [PPC] Replace debug value skipping with getLastNonDebugInstr.Benjamin Kramer2015-06-251-16/+7
| | | | | | No functionality change intended. llvm-svn: 240641
* Replace copy-pasted debug value skipping with MBB::getLastNonDebugInstrBenjamin Kramer2015-06-254-48/+20
| | | | | | No functional change intended. llvm-svn: 240639
* [mips] [IAS] Refactor the emitDirectiveModuleFP() functions. NFC.Toma Tabacu2015-06-253-28/+25
| | | | | | | | | | | | | | | | | | | | Summary: Simplify emitDirectiveModuleFP() by having it just print the current information from MipsABIFlagsSection and doing an updateABIInfo() before such calls. This prevents us from forgetting to update the STI.FeatureBits, because updateABIInfo() uses those to update the MipsABIFlagsSection object, and also makes sure we use the update mechanism from MipsABIFlagsSection. Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits, mpf Differential Revision: http://reviews.llvm.org/D10642 llvm-svn: 240637
* Take alignment into account in isSafeToLoadUnconditionallyArtur Pilipenko2015-06-251-6/+20
| | | | | | | | Reviewed By: hfinkel Differential Revision: http://reviews.llvm.org/D10475 llvm-svn: 240636
* [SystemZ] Only attempt RxSBG optimization for integer typesUlrich Weigand2015-06-251-2/+7
| | | | | | | | | | | | As pointed out by Justin Bogner (see r240520), SystemZDAGToDAGISel::Select currently attempts to convert boolean operations into RxSBG even on some non-integer types (in particular, vector types). This would not work in any case, and it happened to trigger undefined behaviour in allOnes. This patch verifies that we have a (<= 64-bit) integer type before attempting to perform this optimization. llvm-svn: 240634
* [mips] [IAS] Refactor the emitDirectiveModuleOddSPReg() functions. NFC.Toma Tabacu2015-06-254-22/+26
| | | | | | | | | | | | | | | | | | | Summary: We can simplify emitDirectiveModuleOddSPReg() by having it print the current OddSPReg information from MipsABIFlagsSection and doing an updateABIInfo() before such calls. This prevents us from forgetting to update the STI.FeatureBits, because updateABIInfo() uses those to update the MipsABIFlagsSection object, and also makes sure we use the update mechanism from MipsABIFlagsSection. Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits, mpf Differential Revision: http://reviews.llvm.org/D10641 llvm-svn: 240630
* Teach LLVM about the PPC64 memory sanitizer implementation.Jay Foad2015-06-251-0/+17
| | | | | | | | | | | | | | | | Summary: This is the LLVM part of the PPC memory sanitizer implementation in D10648. Reviewers: kcc, samsonov, willschm, wschmidt, eugenis Reviewed By: eugenis Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D10649 llvm-svn: 240627
* [mips] [IAS] Fix parsing of memory offset expressions with parenthesis depth >1.Toma Tabacu2015-06-252-2/+28
| | | | | | | | | | | | | | | | | | | Summary: In an expression such as "(((a+b)+c)+d)", parseParenExpression() would only parse the "a+b)+c", which would result in an error later on in the parser. This means that we can only parse one level of inner parentheses. In order to fix this, I added a new function called parseParenExprOfDepth(), which parses a specified number of trailing parenthesis expressions (except for the outermost parenthesis), and changed MipsAsmParser to use it in parseMemOffset instead of parseParenExpression(). Reviewers: dsanders, rafael Reviewed By: dsanders, rafael Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D9742 llvm-svn: 240625
* [X86] Accept hasAVX512() as well as hasFMA() when generating FMA.Ahmed Bougacha2015-06-251-3/+5
| | | | | | | | | | We don't always have FMA, for example when using 'clang -mavx512f' without an explicit CPU. Also check for an explicit +avx512f instead of CPUs in a couple related tests. llvm-svn: 240616
* Enable StackMap Serialization for COFFSwaroop Sridhar2015-06-252-0/+7
| | | | | | | | | | | | | | | | | | Summary This change turns on the emission of __LLVM_Stackmaps section when generating COFF binaries. Test Plan Added a scenario to the test case: test\CodeGen\X86\statepoint-stackmap-format.ll. Code Review: http://reviews.llvm.org/D10680 llvm-svn: 240613
* libObject/COFF: Add a function to get pointers to relocation entries.Rui Ueyama2015-06-251-0/+10
| | | | llvm-svn: 240610
* Add simplify_type<const WeakVH>; simplify IndVarSimplifyDuncan P. N. Exon Smith2015-06-241-4/+3
| | | | | | | | r240214 fixed some UB in IndVarSimplify, and it needed a temporary `WeakVH` to do it. Add `simplify_type<const WeakVH>` so that this temporary isn't necessary. llvm-svn: 240599
* [X86] Simplify some stuff in X86DisassemblerDecoder. NFCDouglas Katzman2015-06-241-22/+17
| | | | | | | | | | | | | | - Deciding that insn->sibIndex is SIB_INDEX_NONE does not require another check beyond the fully decoded bits being equal to 0x4. The expression insn->sibIndex == SIB_INDEX_sib could not have been true unless index were 0x4, because SIB_INDEX_sib is merely the range base (SIB_INDEX_EAX) plus 4. Respectively SIB_INDEX_sib64. - Don't use a switch statement to perform left-shift. Differential Revision: http://reviews.llvm.org/D9762 llvm-svn: 240598
* [GVN] Intersect the IR flags when CSE'ing two instructionsDavid Majnemer2015-06-241-7/+3
| | | | | | | | | We performed a simple, but incomplete, intersection when it came time to CSE instructions. It didn't handle, for example, the 'exact' flag. This fixes PR23922. llvm-svn: 240595
* [Reassociate] Don't propogate flags when creating negationsDavid Majnemer2015-06-241-0/+10
| | | | | | | | | Reassociate mutated existing instructions in order to form negations which would create additional reassociate opportunities. This fixes PR23926. llvm-svn: 240593
* fix typos; NFCSanjay Patel2015-06-241-3/+2
| | | | llvm-svn: 240592
* don't repeat function names in comments; NFCSanjay Patel2015-06-242-106/+91
| | | | llvm-svn: 240591
* [If Converter] Convert recursion to iteration.Akira Hatanaka2015-06-241-126/+155
| | | | | | | | | | | | | | | | | | | | | | | | | | | This commit makes changes to IfConverter::AnalyzeBlock to use iteration instead of recursion. Previously, this function would get called recursively a large number of times and eventually segfault when a function with the following CFG was compiled: BB0: if (condition0) goto BB1 goto BB2 BB1: goto BB2 BB2: if (condition1) goto BB3 goto BB4 BB3: ... (repeat until BB7488) rdar://problem/21386145 Differential Revision: http://reviews.llvm.org/D10587 llvm-svn: 240589
* Devirtualize Instruction::clone_implPete Cooper2015-06-242-49/+57
| | | | llvm-svn: 240588
* Add NVPTXPeephole pass to reduce unnecessary address castJingyue Wu2015-06-246-16/+178
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: This patch first change the register that holds local address for stack frame to %SPL. Then the new NVPTXPeephole pass will try to scan the following pattern %vreg0<def> = LEA_ADDRi64 <fi#0>, 4 %vreg1<def> = cvta_to_local %vreg0 and transform it into %vreg1<def> = LEA_ADDRi64 %VRFrameLocal, 4 Patched by Xuetian Weng Test Plan: test/CodeGen/NVPTX/local-stack-frame.ll Reviewers: jholewinski, jingyue Reviewed By: jingyue Subscribers: eliben, jholewinski, llvm-commits Differential Revision: http://reviews.llvm.org/D10549 llvm-svn: 240587
* fix typos; NFCSanjay Patel2015-06-241-2/+2
| | | | llvm-svn: 240585
* ARMLoadStoreOptimizer: Fix errata 602117 handling and make testcase actually ↵Matthias Braun2015-06-241-107/+112
| | | | | | | | | | test for it This fixes PR23912 Differential Revision: http://reviews.llvm.org/D10620 llvm-svn: 240582
* Make computeSymbolSizes never fail.Rafael Espindola2015-06-243-15/+45
| | | | | | | | | | | On ELF that was already the case since getting the size of a symbol never fails. On MachO and COFF we could fail trying to get the section of a symbol. But we don't really need the section, just the section number to know if two symbols are in the same section or not. llvm-svn: 240580
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