summaryrefslogtreecommitdiffstats
path: root/llvm/lib
diff options
context:
space:
mode:
authorMatthias Braun <matze@braunis.de>2015-06-26 00:26:49 +0000
committerMatthias Braun <matze@braunis.de>2015-06-26 00:26:49 +0000
commit7c6d6491dd21893d0819ebdcb7b3b5d495c2f7c0 (patch)
tree3951814d28b0c88809c8e12fdf3a6eb2adb91558 /llvm/lib
parentf3518215f75fdcbf7a8e844fc09dce4d3a3b4e48 (diff)
downloadbcm5719-llvm-7c6d6491dd21893d0819ebdcb7b3b5d495c2f7c0.tar.gz
bcm5719-llvm-7c6d6491dd21893d0819ebdcb7b3b5d495c2f7c0.zip
Revert "X86: Reject register operands with obvious type mismatches."
Revert until http://llvm.org/PR23955 is investigated. This reverts commit r239309. llvm-svn: 240746
Diffstat (limited to 'llvm/lib')
-rw-r--r--llvm/lib/Target/X86/X86ISelLowering.cpp13
1 files changed, 0 insertions, 13 deletions
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index 105c2ddfd9e..47d107607e6 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -25583,10 +25583,6 @@ X86TargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
Res.first = DestReg;
Res.second = &X86::GR64RegClass;
}
- } else if (VT != MVT::Other) {
- // Type mismatch and not a clobber: Return an error;
- Res.first = 0;
- Res.second = nullptr;
}
} else if (Res.second == &X86::FR32RegClass ||
Res.second == &X86::FR64RegClass ||
@@ -25612,15 +25608,6 @@ X86TargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
Res.second = &X86::VR256RegClass;
else if (X86::VR512RegClass.hasType(VT))
Res.second = &X86::VR512RegClass;
- else if (VT != MVT::Other) {
- // Type mismatch and not a clobber: Return an error;
- Res.first = 0;
- Res.second = nullptr;
- }
- } else if (VT != MVT::Other) {
- // Type mismatch and not a clobber: Return an error;
- Res.first = 0;
- Res.second = nullptr;
}
return Res;
OpenPOWER on IntegriCloud