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* [ARM] Select result 1 from ConvertBooleanCarryToCarryFlag's result ↵Amaury Sechet2018-05-071-4/+6
| | | | | | | | automatically. NFC The old behavior return the value 0, which is error prone. llvm-svn: 331614
* [TargetLowering] Use StringRef::split instead of SplitString. NFCCraig Topper2018-05-071-2/+2
| | | | | | SplitString splits based on a list of delimeters, but we're only using one delimeter so we should use the simpler split. llvm-svn: 331613
* [X86] Fix copy/paste mistake in comment. NFCCraig Topper2018-05-071-1/+1
| | | | llvm-svn: 331611
* [NFC][DAGCombine] unfoldMaskedMerge(): rename two variablesRoman Lebedev2018-05-061-4/+4
| | | | | | | The current names can be confused with the A and B sides of the canonical masked merge pattern. llvm-svn: 331609
* [X86] Enable reciprocal estimates for v16f32 vectors by using ↵Craig Topper2018-05-061-6/+10
| | | | | | | | | | | | | | | | | | | VRCP14PS/VRSQRT14PS Summary: The legacy VRCPPS/VRSQRTPS instructions aren't available in 512-bit versions. The new increased precision versions are. So we can use those to implement v16f32 reciprocal estimates. For KNL CPUs we can probably use VRCP28PS/VRSQRT28PS and avoid the NR step altogether, but I leave that for a future patch. Reviewers: spatel Reviewed By: spatel Subscribers: RKSimon, llvm-commits, mehdi_amini Differential Revision: https://reviews.llvm.org/D46498 llvm-svn: 331606
* [globalisel] Update GlobalISel emitter to match new representation of ↵Daniel Sanders2018-05-052-4/+37
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | extending loads Summary: Previously, a extending load was represented at (G_*EXT (G_LOAD x)). This had a few drawbacks: * G_LOAD had to be legal for all sizes you could extend from, even if registers didn't naturally hold those sizes. * All sizes you could extend from had to be allocatable just in case the extend went missing (e.g. by optimization). * At minimum, G_*EXT and G_TRUNC had to be legal for these sizes. As we improve optimization of extends and truncates, this legality requirement would spread without considerable care w.r.t when certain combines were permitted. * The SelectionDAG importer required some ugly and fragile pattern rewriting to translate patterns into this style. This patch changes the representation to: * (G_[SZ]EXTLOAD x) * (G_LOAD x) any-extends when MMO.getSize() * 8 < ResultTy.getSizeInBits() which resolves these issues by allowing targets to work entirely in their native register sizes, and by having a more direct translation from SelectionDAG patterns. Each extending load can be lowered by the legalizer into separate extends and loads, however a target that supports s1 will need the any-extending load to extend to at least s8 since LLVM does not represent memory accesses smaller than 8 bit. The legalizer can widenScalar G_LOAD into an any-extending load but sign/zero-extending loads need help from something else like a combiner pass. A follow-up patch that adds combiner helpers for for this will follow. The new representation requires that the MMO correctly reflect the memory access so this has been corrected in a couple tests. I've also moved the extending loads to their own tests since they are (mostly) separate opcodes now. Additionally, the re-write appears to have invalidated two tests from select-with-no-legality-check.mir since the matcher table no longer contains loads that result in s1's and they aren't legal in AArch64 anymore. Depends on D45540 Reviewers: ab, aditya_nandakumar, bogner, rtereshin, volkan, rovka, javed.absar Reviewed By: rtereshin Subscribers: javed.absar, llvm-commits, kristof.beyls Differential Revision: https://reviews.llvm.org/D45541 llvm-svn: 331601
* [MIRPraser] Improve error checking for typed immediate operandsHeejin Ahn2018-05-051-6/+13
| | | | | | | | | | | | | | Summary: This improves error checks for typed immediate operands introduced in D45948 (rL331586), and removes a code block copied by mistake. Reviewers: rtereshin Subscribers: dschuff, sbc100, jgravelle-google, llvm-commits Differential Revision: https://reviews.llvm.org/D46491 llvm-svn: 331600
* Simplify LLVM_ATTRIBUTE_USED call sites.Fangrui Song2018-05-053-15/+7
| | | | llvm-svn: 331599
* [DAGCombiner] Masked merge: don't touch "not" xor's.Roman Lebedev2018-05-051-0/+10
| | | | | | | | | | | | | | | | | | | | Summary: Split off form D46031. It seems we don't want to transform the pattern if the `xor`'s are actually `not`'s. In vector case, this breaks `andnpd` / `vandnps` patterns. That being said, we may want to re-visit this `not` handling, maybe in D46073. Reviewers: spatel, craig.topper, javed.absar Reviewed By: spatel Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D46492 llvm-svn: 331595
* [LTO] Handle Task=-1 passed to addSaveTempsTeresa Johnson2018-05-051-3/+5
| | | | | | | | | | | | | | | | | | | Summary: This change is necessary for D46464, which will pass -1 as the Task ID for distributed backends, so that the save temps files don't end up with "4294967295" in their path. For distributed back ends, when -1 is passed, don't append any Task ID. An existing test (tools/clang/test/CodeGen/thinlto_backend.ll) will fail without this change after D46464. Reviewers: pcc Subscribers: mehdi_amini, inglorion, llvm-commits Differential Revision: https://reviews.llvm.org/D46488 llvm-svn: 331591
* [NFC][DagCombiner] unfoldMaskedMerge(): improve readability.Roman Lebedev2018-05-051-4/+4
| | | | llvm-svn: 331588
* [CaptureTracking] Handle capturing of launder.invariant.groupPiotr Padlewski2018-05-051-22/+23
| | | | | | | | | | | | | | | | | | Summary: launder.invariant.group has the same rules of capturing as bitcast, gep, etc - the original value is not captured if the returned pointer is not captured. With this patch, we mark 40% more functions as noalias when compiling with -fstrict-vtable-pointers; 1078 vs 1778 (39.37%) Reviewers: sanjoy, davide, nlewycky, majnemer, mehdi_amini Subscribers: JDevlieghere, llvm-commits Differential Revision: https://reviews.llvm.org/D32673 llvm-svn: 331587
* [MIRParser] Allow register class names in the form of integer/scalarHeejin Ahn2018-05-053-29/+18
| | | | | | | | | | | | | | | | Summary: The current code cannot handle register class names like 'i32', which is a valid register class name in WebAssembly. This patch removes special handling for integer/scalar/pointer type parsing and treats them as normal identifiers. Reviewers: thegameg Subscribers: jfb, dschuff, sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D45948 llvm-svn: 331586
* Range-ify for loop; NFCGeorge Burgess IV2018-05-051-2/+1
| | | | llvm-svn: 331582
* Fix a bunch of places where operator-> was used directly on the return from ↵Craig Topper2018-05-0514-26/+24
| | | | | | | | | | dyn_cast. Inspired by r331508, I did a grep and found these. Mostly just change from dyn_cast to cast. Some cases also showed a dyn_cast result being converted to bool, so those I changed to isa. llvm-svn: 331577
* LowerTypeTests: Fix non-determinism in code that handles icall branch funnels.Peter Collingbourne2018-05-051-13/+26
| | | | | | | | | This was exposed by enabling expensive checks, which causes llvm::sort to sort randomly. Differential Revision: https://reviews.llvm.org/D45901 llvm-svn: 331573
* [LTO] Allow pass remarks with hotness to be set when emitting to stderrTeresa Johnson2018-05-041-2/+2
| | | | | | | | | | | | | | | | | | | | | Summary: Set setDiagnosticsHotnessRequested before the early exit check for a diagnostic output file, so that pass remarks with hotness works when emitting pass remarks to stderr (e.g. via -pass-remarks=.). Also fix the llvm-lto2 diagnistic handler so that it only calls exit(1) when the diagnistic is an error type. Otherwise the new test invocation of llvm-lto2 with -pass-remarks causes it to fail. The new code is consistent with the diagnostic handler elsewhere (e.g. on the LLVMContext). Reviewers: pcc, davide Subscribers: fhahn, mehdi_amini, llvm-commits, inglorion Differential Revision: https://reviews.llvm.org/D46387 llvm-svn: 331569
* Mapping SDNode flags to MachineInstr flagsMichael Berg2018-05-041-1/+26
| | | | | | | | | | | | | | Summary: Providing the glue to map SDNode fast math sub flags to MachineInstr fast math sub flags. Reviewers: spatel, arsenm, wristow Reviewed By: spatel Subscribers: wdng Differential Revision: https://reviews.llvm.org/D46447 llvm-svn: 331567
* AMDGPU/NFC: Update D16PreservesUnusedBits description based Tony Tye's commentsKonstantin Zhuravlyov2018-05-041-1/+3
| | | | llvm-svn: 331564
* [LICM] Compute a must execute property for the prefix of the header as we goPhilip Reames2018-05-041-3/+14
| | | | | | | | Computing this property within the existing walk ensures that the cost is linear with the size of the block. If we did this from within isGuaranteedToExecute, it would be quadratic without some very fancy caching. This allows us to reliably catch a hoistable instruction within a header which may throw at some point *after* our hoistable instruction. It doesn't do anything for non-header cases, but given how common single block loops are, this seems very worthwhile. llvm-svn: 331557
* AMDGPU/NFC: Fix formatting for 900, 902 ISA Version featuresKonstantin Zhuravlyov2018-05-041-4/+2
| | | | llvm-svn: 331553
* AMDGPU: Add D16 instructions preserve unused bits featureKonstantin Zhuravlyov2018-05-046-9/+27
| | | | | | | | | - Predicate D16 patterns on this new feature - Added this new feature to gfx900/2/4 Differential Revision: https://reviews.llvm.org/D46366 llvm-svn: 331551
* [MachineLICM] Debug intrinsics shouldn't affect hoist decisionsGeoff Berry2018-05-041-0/+4
| | | | | | | | | | | | | | | | Summary: When checking if an instruction stores to a given frame index, check that the instruction can write to memory before looking at the memory operands list to avoid e.g. DBG_VALUE instructions that reference a frame index preventing a load from that index from being hoisted. Reviewers: dblaikie, MatzeB, qcolombet, reames, javed.absar Subscribers: mcrosier, llvm-commits Differential Revision: https://reviews.llvm.org/D46284 llvm-svn: 331549
* [ObjCARC] Account for catchswitch in bitcast insertionShoaib Meenai2018-05-041-4/+17
| | | | | | | | | | | | | A catchswitch is both a pad and a terminator, meaning it must be the only non-phi instruction in its basic block. When we're inserting a bitcast in the incoming basic block for a phi, if that incoming block is a catchswitch, we should go up the dominator tree to find a valid insertion point rather than attempting to insert before the catchswitch (which would result in invalid IR). Differential Revision: https://reviews.llvm.org/D46412 llvm-svn: 331548
* Fast Math Flag mapping into SDNodeMichael Berg2018-05-045-15/+18
| | | | | | | | | | | | | | Summary: Adding support for Fast flags in the SDNode to leverage fast math sub flag usage. Reviewers: spatel, arsenm, jbhateja, hfinkel, escha, qcolombet, echristo, wristow, javed.absar Reviewed By: spatel Subscribers: llvm-commits, rampitec, nhaehnle, tstellar, FarhanaAleen, nemanjai, javed.absar, jbhateja, hfinkel, wdng Differential Revision: https://reviews.llvm.org/D45710 llvm-svn: 331547
* [X86] Add WriteEMMS scheduler classSimon Pilgrim2018-05-0412-34/+15
| | | | | | Filled in the missing values from Btver2 SoG or Agner llvm-svn: 331546
* [X86] Finish splitting WriteVecShift and WriteVecIMul to remove InstRW ↵Simon Pilgrim2018-05-0411-103/+44
| | | | | | overrides. llvm-svn: 331543
* [LoopIdiomRecognize] Don't create an IRBuilder just to call getTrue/getFalse.Craig Topper2018-05-041-2/+2
| | | | | | We can call the methods in ConstantInt directly. We just need a context. llvm-svn: 331542
* DwarfCompileUnit: Fix another assertion failure on malformed inputAdrian Prantl2018-05-042-1/+2
| | | | | | | | that is not rejected by the Verifier. Thanks to Björn Pettersson for providing a reproducer! llvm-svn: 331535
* [llvm-exegesis] Fix pfm counter names for BDW.Clement Courbet2018-05-041-8/+8
| | | | | | | | | | | | Summary: They are not consistent with other microarchitectures. Reviewers: gchatelet Subscribers: tschuett, llvm-commits Differential Revision: https://reviews.llvm.org/D46434 llvm-svn: 331532
* [X86] Cleanup SchedWriteFMA classes and use X86SchedWriteWidths directly.Simon Pilgrim2018-05-0412-82/+80
| | | | | | Rename scalar and XMM versions, this is to match/simplify an upcoming change to split MUL/DIV/SQRT scalar/xmm/ymm/zmm classes. llvm-svn: 331531
* [Hexagon] Remove leftover debugging code after r331527Krzysztof Parzyszek2018-05-041-1/+0
| | | | llvm-svn: 331528
* [Hexagon] Handle non-immediate constants in HexagonSplitDoubleKrzysztof Parzyszek2018-05-042-24/+28
| | | | llvm-svn: 331527
* [mips] Correct the predicates of sign extension instructionsSimon Dardis2018-05-044-29/+5
| | | | | | | | | | And eliminatw the duplication of those instructions for microMIPS32r6. Reviewers: smaksimovic, abeserminji, atanasyan Differential Revision: https://reviews.llvm.org/D46117 llvm-svn: 331526
* [X86] Add WriteVecMOVMSKY scheduler classSimon Pilgrim2018-05-0411-40/+48
| | | | llvm-svn: 331525
* [AArch64] Custom Lower MULLH{S,U} for v16i8, v8i16, and v4i32Adhemerval Zanella2018-05-042-2/+89
| | | | | | | | | | | | | | This patch adds a custom lowering for ISD::MULH{S,U} used on divide by constant optimization (DAGCombiner::BuildSDIV and DAGCombiner::BuildUDIV). New patterns for smull and umull are added, so AArch64ISD::{S,U}MULL can be correctly lowered to smull2 and umull2. Reviewed By: SjoerdMeijer Differential Revision: https://reviews.llvm.org/D46009 llvm-svn: 331522
* [Hexagon] Skip reserved physical registers when updating livenessKrzysztof Parzyszek2018-05-041-1/+8
| | | | llvm-svn: 331518
* [X86] Add SchedWriteFRnd fp rounding scheduler classesSimon Pilgrim2018-05-0413-164/+67
| | | | | | | | Split off from SchedWriteFAdd for fp rounding/bit-manipulation instructions. Fixes an issue on btver2 which only had the ymm version using the JSTC pipe instead of JFPA. llvm-svn: 331515
* [SelectionDAG] Refactor code by adding RegsForValue::getRegsAndSizes(). NFCIBjorn Pettersson2018-05-042-40/+43
| | | | | | | | | | | | | | | | | | Summary: Added a helper method in RegsForValue to get a list with all the <RegNumber, RegSize> pairs that we want to iterate over in SelectionDAGBuilder::EmitFuncArgumentDbgValue and in SelectionDAGBuilder::visitIntrinsicCall. Reviewers: vsk Reviewed By: vsk Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D46360 llvm-svn: 331510
* [RegUsageInfoCollector] Bugfix for handling of register aliases.Jonas Paulsson2018-05-041-7/+6
| | | | | | | | | | | | | | | | | Don't assume the alias of a defined reg is always already in the set. As the test case in https://bugs.llvm.org/show_bug.cgi?id=36587 discovered, it is wrong to assume that all the aliases of the defined register in the *current function* is already present in the UsedPhysRegsMask. This patch changes this so that any definition in the current function of a phys-reg always results in all its aliases inserted into the set of defined registers. Review: Quentin Colombet https://reviews.llvm.org/D45157 llvm-svn: 331509
* [IRCE] Fix misuse of dyn_cast which leads to UBMax Kazantsev2018-05-041-2/+3
| | | | llvm-svn: 331508
* [MachineCSE] Rewrite a loop checking if a block is in a set of blocks ↵Michael Zolotukhin2018-05-041-7/+5
| | | | | | | | | | | | | | | | | | without using a set. NFC. Summary: Using a set is unnecessary here an in some cases (see e.g. PR37277) takes significant amount of time to just insert values into it. In this particular case all we need is just to check if we find the block we are looking for or not. Reviewers: davide Subscribers: hiraditya, llvm-commits Differential Revision: https://reviews.llvm.org/D46411 llvm-svn: 331502
* [LoopIdiomRecognize] Replace more unchecked dyn_casts with cast.Craig Topper2018-05-041-4/+4
| | | | | | Two of these are immediately dereferenced on the next line. The other two are passed immediately to the IRBuilder constructor which can't handle a nullptr. llvm-svn: 331500
* [LoopIdiomRecognize] Use a regular array instead of a SmallVector and ↵Craig Topper2018-05-041-2/+1
| | | | | | explicit ArrayRef. llvm-svn: 331499
* [LoopIdiomRecognize] Turn two uncheck dyn_casts into regular casts.Craig Topper2018-05-041-2/+2
| | | | | | These are casts on users of a PHINode to Instruction. I think since PHINode is an Instruction any users would also be Instructions. At least a cast will give us an assertion if its wrong. llvm-svn: 331498
* AMDGPU: Make getSubRegFromChannel a static member of AMDGPURegisterInfoTom Stellard2018-05-035-9/+9
| | | | | | | | | | | | | | | | Summary: This makes is possible to have R600RegisterInfo and SIRegisterInfo not inherit from AMDGPURegisterInfo. Reviewers: arsenm, nhaehnle Reviewed By: arsenm Subscribers: kzhuravl, wdng, yaxunl, dstuttard, tpr, llvm-commits, t-tye Differential Revision: https://reviews.llvm.org/D46280 llvm-svn: 331490
* [X86] Add WriteDPPD/WriteDPPS dot product scheduler classesSimon Pilgrim2018-05-0311-232/+42
| | | | llvm-svn: 331489
* [X86][Znver1] Use SchedAlias to tag microcoded scheduler classesSimon Pilgrim2018-05-031-32/+30
| | | | | | | | Avoids extra entries in the class tables. Found a typo that missed the MMX_PHSUBSW instruction. llvm-svn: 331488
* Fix include of config.h that was incorrectly changed in r331184Justin Bogner2018-05-031-1/+1
| | | | | | | | | The RWMutex implementation depends on config.h macros (specifically HAVE_PTHREAD_H and HAVE_PTHREAD_RWLOCK_INIT), so we need to be including it and not just llvm-config.h here or we fall back to a much slower implementation. llvm-svn: 331487
* [InstCombine] refine select-of-constants to bitwise opsSanjay Patel2018-05-031-57/+34
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add logic for the special case when a cmp+select can clearly be reduced to just a bitwise logic instruction, and remove an over-reaching chunk of general purpose bit magic. The primary goal is to remove cases where we are not improving the IR instruction count when doing these select transforms, and in all cases here that is true. In the motivating 3-way compare tests, there are further improvements because we can combine/propagate select values (not sure if that belongs in instcombine, but it's there for now). DAGCombiner has folds to turn some of these selects into bit magic, so there should be no difference in the end result in those cases. Not all constant combinations are handled there yet, however, so it is possible that some targets will see more cmov/csel codegen with this change in IR canonicalization. Ideally, we'll go further to *not* turn selects into multiple logic/math ops in instcombine, and we'll canonicalize to selects. But we should make sure that this step does not result in regressions first (and if it does, we should fix those in the backend). The general direction for this change was discussed here: http://lists.llvm.org/pipermail/llvm-dev/2016-September/105373.html http://lists.llvm.org/pipermail/llvm-dev/2017-July/114885.html Alive proofs for the new bit magic: https://rise4fun.com/Alive/XG7 Differential Revision: https://reviews.llvm.org/D46086 llvm-svn: 331486
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