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* CPSR can be livein; transfer predicate operands correctly; tMUL is two-address.Evan Cheng2009-08-101-19/+57
| | | | llvm-svn: 78559
* Add support for folding loads / stores into 16-bit moves used by Thumb2.Evan Cheng2009-08-101-37/+61
| | | | llvm-svn: 78558
* 80 col violation.Evan Cheng2009-08-101-2/+3
| | | | llvm-svn: 78557
* Use tMOVgpr2gpr instead of t2MOVr.Evan Cheng2009-08-101-4/+7
| | | | llvm-svn: 78556
* Add support for a user supplied pointer argument to llvm_install_error_handler.Daniel Dunbar2009-08-101-2/+6
| | | | llvm-svn: 78553
* Move ConstantExpr handling to ResolveConstantExpr method and alsoBruno Cardoso Lopes2009-08-102-28/+87
| | | | | | add support for PtrToInt, Add, Mul. llvm-svn: 78552
* Add support to reduce most of 32-bit Thumb2 arithmetic instructions.Evan Cheng2009-08-104-81/+161
| | | | llvm-svn: 78550
* Always use the 16-bit tMOVgpr2gpr instead of the 32-bit t2MOVr.Evan Cheng2009-08-101-2/+1
| | | | llvm-svn: 78549
* Make the big switch: Change MCSectionMachO to represent a section *semantically*Chris Lattner2009-08-106-123/+429
| | | | | | | | | | | | | | | | instead of syntactically as a string. This means that it keeps track of the segment, section, flags, etc directly and asmprints them in the right format. This also includes parsing and validation support for llvm-mc and "attribute(section)", so we should now start getting errors about invalid section attributes from the compiler instead of the assembler on darwin. Still todo: 1) Uniquing of darwin mcsections 2) Move all the Darwin stuff out to MCSectionMachO.[cpp|h] 3) there are a few FIXMEs, for example what is the syntax to get the S_GB_ZEROFILL segment type? llvm-svn: 78547
* Use abs64 instead abs; some platforms don't have a 64-bit abs overload. ↵Benjamin Kramer2009-08-091-1/+1
| | | | | | Noticed by Yonggang Luo! llvm-svn: 78543
* Add support to convert 32-bit instructions to 16-bit non-two-address ones.Evan Cheng2009-08-091-35/+96
| | | | llvm-svn: 78540
* always end a section with \n on elf.Chris Lattner2009-08-091-0/+2
| | | | llvm-svn: 78534
* llvm-mc/AsmParser: Implement user defined super classes.Daniel Dunbar2009-08-092-2/+27
| | | | | | - We can now discriminate SUB32ri8 from SUB32ri, for example. llvm-svn: 78530
* Extend comment on ParserMatchClass .td field, and add some missingDaniel Dunbar2009-08-092-0/+4
| | | | | | classes for X86. llvm-svn: 78524
* llvm-mc/AsmParser: Define match classes in the .td file.Daniel Dunbar2009-08-091-0/+3
| | | | | | -2 FIXMEs. llvm-svn: 78523
* sink the 'name' and 'isdirective' state out of MCSection into its derived ↵Chris Lattner2009-08-088-84/+106
| | | | | | | | classes. This totally optimizes PIC16 sections by not having an 'isdirective' bit anymore!! ;-) llvm-svn: 78517
* Use subclassing to print lane-like immediates (w/o hash) eliminatingAnton Korobeynikov2009-08-085-32/+37
| | | | | | 'no_hash' modifier. Hopefully this will make Daniel happy :) llvm-svn: 78514
* add a note about dead zero extends.Chris Lattner2009-08-081-0/+49
| | | | llvm-svn: 78511
* 1. Make MCSection an abstract class.Chris Lattner2009-08-088-123/+120
| | | | | | | | | 2. Move section switch printing to MCSection virtual method which takes a TAI. This eliminates textual formatting stuff from TLOF. 3. Eliminate SwitchToSectionDirective, getSectionFlagsAsString, and TLOFELF::AtIsCommentChar. llvm-svn: 78510
* Add crc32 instruction and intrinsics. Add a new class of prefixEric Christopher2009-08-085-0/+93
| | | | | | | | | bytes for F2 0F 38 and propagate. Add a FIXME for a set of possibilities which correspond to intrinsics already used. New test. llvm-svn: 78508
* Add support for READCYCLECOUNTER in Blackfin back-end.Jakob Stoklund Olesen2009-08-083-0/+35
| | | | llvm-svn: 78506
* add new PIC16Section class, this time hopefully not breaking the build :)Chris Lattner2009-08-083-2/+40
| | | | llvm-svn: 78505
* llvm-mc/AsmMatcher: Switch token matching to use the new string matcher.Daniel Dunbar2009-08-081-2/+6
| | | | | | | Also, redefined MatchRegisterName to just return the register value or a sentinel, to simplify the generated code. llvm-svn: 78504
* Revert r78501, it doesn't build.Daniel Dunbar2009-08-082-37/+1
| | | | | | | | --- Reverse-merging r78501 into '.': U lib/Target/PIC16/PIC16TargetObjectFile.cpp D lib/Target/PIC16/PIC16Section.h llvm-svn: 78503
* make PIC16 create its own custom MCSection.Chris Lattner2009-08-082-1/+37
| | | | llvm-svn: 78501
* make target-specific TLOF impls (except PIC16) create target-specificChris Lattner2009-08-082-5/+5
| | | | | | MCSection instances. llvm-svn: 78500
* stub out PECOFF/MachO/ELF MCSection classesChris Lattner2009-08-081-2/+20
| | | | llvm-svn: 78499
* eliminate TargetLoweringObjectFileSparc in favor of a TAI hook.Chris Lattner2009-08-085-31/+28
| | | | | | | | A TAI hook is appropriate in this case because this is just an asm syntax issue, not a semantic difference. TLOF should model the semantics of the section. llvm-svn: 78498
* Don't build illegal ops in DAGCombiner::SimplifyBinOpWithSameOpcodeHands().Jakob Stoklund Olesen2009-08-081-1/+3
| | | | | | | | Blackfin supports and/or/xor on i32 but not on i16. Teach DAGCombiner::SimplifyBinOpWithSameOpcodeHands to not produce illegal nodes after legalize ops. llvm-svn: 78497
* give pic16 a target-specific section creation name tooChris Lattner2009-08-082-35/+33
| | | | llvm-svn: 78496
* now that getOrCreateSection is all object-file specific,Chris Lattner2009-08-083-152/+133
| | | | | | | give the impls an object-file-specific name. In the future they can take different arguments etc. llvm-svn: 78495
* sink getOrCreateSection down into all the object file implementations,Chris Lattner2009-08-083-8/+34
| | | | | | now that they create *all* the sections. llvm-svn: 78494
* Some ProfileInfo cleanups.Daniel Dunbar2009-08-082-1/+2
| | | | | | - Part of optimal static profiling patch sequence by Andreas Neustifter. llvm-svn: 78485
* Add a basic static ProfileInfo provider (ProfileEstimatorPass).Daniel Dunbar2009-08-082-0/+237
| | | | | | - Part of optimal static profiling patch sequence by Andreas Neustifter. llvm-svn: 78484
* Use reloc_absolute_word_sext relocation for X86::MOV64(ri/mi)32 ↵Bruno Cardoso Lopes2009-08-081-2/+2
| | | | | | | | | instructions, since they are in 64 bit mode with i64immSExt32 imms. JIT is not affected since it handles both word absolute relocations in the same way llvm-svn: 78479
* More ProfileInfo improvements.Daniel Dunbar2009-08-085-68/+97
| | | | | | | | | | | | - Part of optimal static profiling patch sequence by Andreas Neustifter. - Store edge, block, and function information separately for each functions (instead of in one giant map). - Return frequencies as double instead of int, and use a sentinel value for missing information. llvm-svn: 78477
* ELF improvements:Bruno Cardoso Lopes2009-08-083-58/+94
| | | | | | | | | | | Handle large integers, x86_fp80, ConstantAggregateZero, and two more ConstantExpr: GetElementPtr and IntToPtr Set SHF_MERGE bit for mergeable strings Avoid zero initialized strings to be classified as a bss symbol Don't allow common symbols to be classified as STB_WEAK Add a constant to be used as a global value offset in data relocations llvm-svn: 78476
* Update CMakeDaniel Dunbar2009-08-081-0/+1
| | | | llvm-svn: 78475
* Clean out per-function data after the machine code verifier is done with it.Jakob Stoklund Olesen2009-08-081-0/+8
| | | | | | | | | | | | | | | Also don't dereference old pointers after they have been deleted causing random crashes when enabling the machine code verifier. Ahem... I have not included a test case for the crash. It hapened when enabling the verifier on CodeGen/X86/2009-08-06-branchfolder-crash.ll. The crash depends on an MBB being allocated at the same address as a previously deleted MBB. I don't think that can be reproduced reliably. llvm-svn: 78472
* Add insert_elt / extract_elt patterns for v4f32 stuff.Anton Korobeynikov2009-08-081-19/+30
| | | | | | Did anyone tests v4f32 ever? llvm-svn: 78470
* Lane number should be printed w/o hashAnton Korobeynikov2009-08-082-11/+11
| | | | llvm-svn: 78469
* Use VLDM / VSTM to spill/reload 128-bit Neon registersAnton Korobeynikov2009-08-085-10/+30
| | | | llvm-svn: 78468
* Update the machine code verifier to keep up with the scavenger.Jakob Stoklund Olesen2009-08-081-12/+22
| | | | | | | | | * Cleaner handling of <undef>. * <def> takes precedence over <def,dead>. * Implement the OK-to-redefine-a-register-that-was- live-in-but-has-not-been-used-before rule. llvm-svn: 78467
* Remove RegisterScavenger::isSuperRegUsed(). This completely reverses the ↵Jakob Stoklund Olesen2009-08-082-38/+9
| | | | | | | | | | | | | | | mistaken commit r77904. Now there is no special treatment of instructions that redefine part of a super-register. Instead, the super-register is marked with <imp-use,kill> and <imp-def>. For instance, from LowerSubregs on ARM: subreg: CONVERTING: %Q1<def> = INSERT_SUBREG %Q1<undef>, %D1<kill>, 5 subreg: %D2<def> = FCPYD %D1<kill>, 14, %reg0, %Q1<imp-def> subreg: CONVERTING: %Q1<def> = INSERT_SUBREG %Q1, %D0<kill>, 6 subreg: %D3<def> = FCPYD %D0<kill>, 14, %reg0, %Q1<imp-use,kill>, %Q1<imp-def> llvm-svn: 78466
* Simplify RegScavenger::forward a bit more.Jakob Stoklund Olesen2009-08-081-65/+53
| | | | | | | | | | | Verify that early clobber registers and their aliases are not used. All changes to RegsAvailable are now done as a transaction so the order of operands makes no difference. The included test case is from PR4686. It has behaviour that was dependent on the order of operands. llvm-svn: 78465
* move this fp select into a patternAndrew Lenharth2009-08-082-22/+9
| | | | llvm-svn: 78464
* llvm-mc/AsmMatcher: Improve match code.Daniel Dunbar2009-08-081-23/+1
| | | | | | | | | | | | | | - This doesn't actually improve the algorithm (its still linear), but the generated (match) code is now fairly compact and table driven. Still need a generic string matcher. - The table still needs to be compressed, this is quite simple to do and should shrink it to under 16k. - This also simplifies and restructures the code to make the match classes more explicit, in anticipation of resolving ambiguities. llvm-svn: 78461
* Implement Neon VZIP and VUZP instructions. These are very similar to VTRN,Bob Wilson2009-08-082-16/+70
| | | | | | so I generalized the class for VTRN in the .td file to handle all 3 of them. llvm-svn: 78460
* Implement Neon VTRN instructions. For now, anyway, these are selectedBob Wilson2009-08-082-0/+48
| | | | | | | | directly from the intrinsics produced by the frontend. If it is more convenient to have a custom DAG node for using these to implement shuffles, we can add that later. llvm-svn: 78459
* Add a skeleton Thumb2 instruction size reduction pass.Evan Cheng2009-08-082-1/+219
| | | | llvm-svn: 78456
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