llvm-mc/AsmParser: Implement user defined super classes.

 - We can now discriminate SUB32ri8 from SUB32ri, for example.

llvm-svn: 78530

2 files changed, 27 insertions, 2 deletions

diff --git a/llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp b/llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp
index ea5528a951a..5a42683a494 100644
--- a/llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp
+++ b/llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp
@@ -137,6 +137,19 @@ struct X86Operand {
 
   bool isImm() const { return Kind == Immediate; }
   
+  bool isImmSExt8() const { 
+    // Accept immediates which fit in 8 bits when sign extended, and
+    // non-absolute immediates.
+    if (!isImm())
+      return false;
+
+    if (!getImm().isAbsolute())
+      return true;
+
+    int64_t Value = getImm().getConstant();
+    return Value == (int64_t) (int8_t) Value;
+  }
+  
   bool isMem() const { return Kind == Memory; }
 
   bool isReg() const { return Kind == Register; }
@@ -151,6 +164,12 @@ struct X86Operand {
     Inst.addOperand(MCOperand::CreateMCValue(getImm()));
   }
 
+  void addImmSExt8Operands(MCInst &Inst, unsigned N) {
+    // FIXME: Support user customization of the render method.
+    assert(N == 1 && "Invalid number of operands!");
+    Inst.addOperand(MCOperand::CreateMCValue(getImm()));
+  }
+
   void addMemOperands(MCInst &Inst, unsigned N) {
     assert((N == 4 || N == 5) && "Invalid number of operands!");
 
diff --git a/llvm/lib/Target/X86/X86InstrInfo.td b/llvm/lib/Target/X86/X86InstrInfo.td
index c21cad98df0..80f03e8318c 100644
--- a/llvm/lib/Target/X86/X86InstrInfo.td
+++ b/llvm/lib/Target/X86/X86InstrInfo.td
@@ -212,9 +212,15 @@ def piclabel: Operand<i32> {
 
 // A couple of more descriptive operand definitions.
 // 16-bits but only 8 bits are significant.
-def i16i8imm  : Operand<i16>;
+def i16i8imm  : Operand<i16> {
+  let ParserMatchClass = "ImmSExt8";
+  let ParserMatchSuperClass = "Imm";
+}
 // 32-bits but only 8 bits are significant.
-def i32i8imm  : Operand<i32>;
+def i32i8imm  : Operand<i32> {
+  let ParserMatchClass = "ImmSExt8";
+  let ParserMatchSuperClass = "Imm";
+}
 
 // Branch targets have OtherVT type and print as pc-relative values.
 def brtarget : Operand<OtherVT> {