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* This Reassociate change unintentionally slipped in r222499David Majnemer2014-11-211-7/+0
| | | | llvm-svn: 222500
* SROA: The alloca type isn't a candidate promotion type for vectorsDavid Majnemer2014-11-212-3/+9
| | | | | | | | | | | | The alloca's type is irrelevant, only those types which are used in a load or store of the exact size of the slice should be considered. This manifested as an assertion failure when we compared the various types: we had a size mismatch. This fixes PR21480. llvm-svn: 222499
* [MCJIT] Remove JITEventListener::NotifyFreeingMachineCode. This method is deadLang Hames2014-11-212-22/+0
| | | | | | now that the old JIT has been removed. llvm-svn: 222494
* Add curly braces to workaround an MSVC bug.Zachary Turner2014-11-211-1/+3
| | | | | | MSVC can't parse this pattern for range-based for loops. llvm-svn: 222491
* [X86] Do not custom lower UINT_TO_FP when the target type does notQuentin Colombet2014-11-211-0/+5
| | | | | | | | match the custom lowering. <rdar://problem/19026326> llvm-svn: 222489
* Verifier: Check that all instructions have their parent pointers set upAdrian Prantl2014-11-211-0/+4
| | | | | | | correctly. This helps with catching problems caused by IRBuilder abuse such as the one fixed in CFE r222487. llvm-svn: 222488
* Fix more instances of -Wsentinel on Windows with s/NULL/nullptr/Reid Kleckner2014-11-204-5/+5
| | | | | | Follow up to r221940, where I must not have caught em all. NFC llvm-svn: 222481
* Add out of line virtual destructors to all LLVMTargetMachine subclassesReid Kleckner2014-11-2022-3/+37
| | | | | | | | | | | | | | | | | These recently all grew a unique_ptr<TargetLoweringObjectFile> member in r221878. When anyone calls a virtual method of a class, clang-cl requires all virtual methods to be semantically valid. This includes the implicit virtual destructor, which triggers instantiation of the unique_ptr destructor, which fails because the type being deleted is incomplete. This is just part of the ongoing saga of PR20337, which is affecting Blink as well. Because the MSVC ABI doesn't have key functions, we end up referencing the vtable and implicit destructor on any virtual call through a class. We don't actually end up emitting the dtor, so it'd be good if we could avoid this unneeded type completion work. llvm-svn: 222480
* Update Makefile following directory removal in r222466Mehdi Amini2014-11-201-1/+1
| | | | llvm-svn: 222475
* SimplifyCFG: Refactor GatherConstantCompares() result in a structMehdi Amini2014-11-201-133/+152
| | | | | | | | | | Code seems cleaner and easier to understand this way This is basically r222416, after fixes for MSVC lack of standard support, and a few cleaning (got rid of a warning). Thanks Nakamura Takumi and Nico Weber for the MSVC fixes. llvm-svn: 222472
* [Hexagon] [NFC] Merging InstPrinter directory in to MCTargetDesc since they ↵Colin LeMahieu2014-11-2011-47/+6
| | | | | | have a circular dependency. llvm-svn: 222458
* [MCJIT] Remove JITEventListener::NotifyFunctionEmitted - this method is deadLang Hames2014-11-202-160/+0
| | | | | | now that the legacy JIT has been removed. llvm-svn: 222453
* Fix a trip-count overflow issue in LoopUnroll.Michael Zolotukhin2014-11-201-2/+11
| | | | | | | | | | | | Currently LoopUnroll generates a prologue loop before the main loop body to execute first N%UnrollFactor iterations. Also, this loop is used if trip-count can overflow - it's determined by a runtime check. However, we've been mistakenly optimizing this loop to a linear code for UnrollFactor = 2, not taking into account that it also serves as a safe version of the loop if its trip-count overflows. llvm-svn: 222451
* X86: use the correct alloca symbol for Windows ItaniumSaleem Abdulrasool2014-11-202-2/+8
| | | | | | | Windows itanium targets the MSVCRT, and the stack probe symbol is provided by MSVCRT. This corrects the emission of stack probes on i686-windows-itanium. llvm-svn: 222439
* Make DWARFAcceleratorTable::dump() const.Frederic Riss2014-11-202-9/+12
| | | | | | | | | As dump() methods should be. To allow that, do not store the DWARFFormValue objects used for the dump in the header data. Per Alexey's suggestion! llvm-svn: 222436
* Add missing copyright headers.Frederic Riss2014-11-202-0/+17
| | | | llvm-svn: 222435
* Do not create a replaceable Variables MDNode for function forward decls.Frederic Riss2014-11-201-4/+4
| | | | | | | | These fields would need to be explicitly deleted before we RAUW the temporary node anyway (this was done in cfe commit r222373). Instead, do not create these useless nodes in the first place. llvm-svn: 222434
* Revert r222416, r222422, r222426: the former revision had problems and ↵Timur Iskhodzhanov2014-11-201-150/+136
| | | | | | fixing them introduced bugs llvm-svn: 222428
* Fix a typoTimur Iskhodzhanov2014-11-201-1/+1
| | | | llvm-svn: 222426
* SimplifyCFG.cpp: Tweak to let msc17 compliant.NAKAMURA Takumi2014-11-201-8/+11
| | | | | | | | - Use LLVM_DELETED_FUNCTION. - Don't use member initializers. - Don't use initializer list. llvm-svn: 222422
* SimplifyCFG: Refactor GatherConstantCompares() result in a structMehdi Amini2014-11-201-136/+147
| | | | | | Code seems cleaner and easier to understand this way llvm-svn: 222416
* [ELF] Prevent ARM ELF object writer from generating deprecated relocation ↵Jyoti Allur2014-11-201-1/+1
| | | | | | code R_ARM_PLT32 llvm-svn: 222414
* Fix a typo in a comment.Craig Topper2014-11-201-1/+1
| | | | llvm-svn: 222412
* Remove support for undocumented SpecialCaseList entries.Alexey Samsonov2014-11-201-12/+0
| | | | | | | | | | | | | "global-init", "global-init-src" and "global-init-type" were originally used to blacklist entities in ASan init-order checker. However, they were never documented, and later were replaced by "=init" category. Old blacklist entries should be converted as follows: * global-init:foo -> global:foo=init * global-init-src:bar -> src:bar=init * global-init-type:baz -> type:baz=init llvm-svn: 222401
* [Hexagon] Adding A2_xor instruction with IR selection pattern and test.Colin LeMahieu2014-11-192-6/+6
| | | | llvm-svn: 222399
* Revert "[Reassociate] As the expression tree is rewritten make sure the ↵Chad Rosier2014-11-191-8/+7
| | | | | | | | | | | | | operands are" This reverts commit r222142. This is causing/exposing an execution-time regression in spec2006/gcc and coremark on AArch64/A57/Ofast. Conflicts: test/Transforms/Reassociate/optional-flags.ll llvm-svn: 222398
* [Hexagon] Adding A2_or instruction with IR selection pattern and test.Colin LeMahieu2014-11-192-3/+6
| | | | llvm-svn: 222396
* Try to fix MSVS build after r222384. No intended behavior change.Nico Weber2014-11-191-3/+3
| | | | llvm-svn: 222386
* SimplifyCFG: turn recursive GatherConstantCompares into iterativeMehdi Amini2014-11-191-99/+138
| | | | | | A long sequence of || or && could lead to a stack explosion. llvm-svn: 222384
* RegisterCoalescer: Improve debug messagesMatthias Braun2014-11-191-6/+8
| | | | | | | | | - Show "Considering..." message after flipping so you actually see the final destination vreg as destination. - Add a message on final join, so you can grep for "Success" messages to obtain a list of which register got merged with which. llvm-svn: 222382
* Add a print and verify pass after the RegisterCoalescerMatthias Braun2014-11-191-0/+1
| | | | llvm-svn: 222381
* MachineVerifier: Report register for bad liverangesMatthias Braun2014-11-191-24/+28
| | | | llvm-svn: 222380
* Introduce register dump helperMatthias Braun2014-11-191-0/+9
| | | | llvm-svn: 222379
* AliasSet: Simplify mergeSetInDavid Majnemer2014-11-191-4/+3
| | | | | | No functional change intended. llvm-svn: 222376
* [X86] Improved lowering of v4x32 build_vector dag nodes.Andrea Di Biagio2014-11-191-58/+90
| | | | | | | | | | | | | | | | | | This patch improves the lowering of v4f32 and v4i32 build_vector dag nodes that are known to have at least two non-zero elements. With this patch, a build_vector that performs a blend with zero is converted into a shuffle. This is done to let the shuffle legalizer expand the dag node in a optimal way. For example, if we know that a build_vector performs a blend with zero, we can try to lower it as a movq/blend instead of always selecting an insertps. This patch also improves the logic that lowers a build_vector into a insertps with zero masking. See for example the extra test cases added to test sse41.ll. Differential Revision: http://reviews.llvm.org/D6311 llvm-svn: 222375
* [ADT] Fix PR20728 - Incorrect APFloat::fusedMultiplyAdd results for x86_fp80.Lang Hames2014-11-191-12/+24
| | | | | | | | | | | | | | As detailed at http://llvm.org/PR20728, due to an internal overflow in APFloat::multiplySignificand the APFloat::fusedMultiplyAdd method can return incorrect results for x87DoubleExtended (x86_fp80) values. This commonly manifests as incorrect constant folding of libm fmal calls on x86. E.g. fmal(1.0L, 1.0L, 3.0L) == 0.0L (should be 4.0L) This patch fixes PR20728 by adding an extra bit to the significand for intermediate results of APFloat::multiplySignificand, avoiding the overflow. llvm-svn: 222374
* R600/SI: Make SIInstrInfo::isOperandLegal() more strictTom Stellard2014-11-191-1/+10
| | | | | | | | | | | | A register operand that has a common sub-class with its instruction's defined register class is not always legal. For example, SReg_32 and M0Reg both have a common sub-class, but we can't use an SReg_32 in instructions that expect a M0Reg. This prevents the llvm.SI.sendmsg.ll test from failing when the fold operand pass is added. llvm-svn: 222368
* [mips][micromips] Implement SWM32 and LWM32 instructionsZoran Jovanovic2014-11-1910-6/+288
| | | | | | Differential Revision: http://reviews.llvm.org/D5519 llvm-svn: 222367
* Vectorize a reduction chain feeding into a 'return' statement.Suyog Sarda2014-11-191-0/+15
| | | | | | | | | e.x return (a[0]+b[0]) + (a[1]+b[1]) Differential Revision: http://reviews.llvm.org/D6227 llvm-svn: 222364
* [mips][microMIPS] Fix opcodes of MFHC1 and MTHC1 instructions.Jozef Kolek2014-11-191-4/+4
| | | | | | Differential Revision: http://reviews.llvm.org/D6169 llvm-svn: 222355
* Fix tail recursion eliminationArnaud A. de Grandmaison2014-11-191-3/+25
| | | | | | | | | | | | | | | | | | | | | | When the BasicBlock containing the return instrution has a PHI with 2 incoming values, FoldReturnIntoUncondBranch will remove the no longer used incoming value and remove the no longer needed phi as well. This leaves us with a BB that no longer has a PHI, but the subsequent call to FoldReturnIntoUncondBranch from FoldReturnAndProcessPred will not remove the return instruction (which still uses the result of the call instruction). This prevents EliminateRecursiveTailCall to remove the value, as it is still being used in a basicblock which has no predecessors. The basicblock can not be erased on the spot, because its iterator is still being used in runTRE. This issue was exposed when removing the threshold on size for lifetime marker insertion for named temporaries in clang. The testcase is a much reduced version of peelOffOuterExpr(const Expr*, const ExplodedNode *) from clang/lib/StaticAnalyzer/Core/BugReporterVisitors.cpp. llvm-svn: 222354
* [mips][microMIPS] Implement CodeGen support for 16-bit instruction ADDIUR2.Jozef Kolek2014-11-191-0/+6
| | | | | | Differential Revision: http://reviews.llvm.org/D5800 llvm-svn: 222352
* [mips][microMIPS] Implement CodeGen support for ADDIUS5 instruction.Jozef Kolek2014-11-192-3/+10
| | | | | | Differential Revision: http://reviews.llvm.org/D5799 llvm-svn: 222351
* [mips][microMIPS] Implement LWXS instruction.Jozef Kolek2014-11-192-0/+23
| | | | | | Differential Revision: http://reviews.llvm.org/D5407 llvm-svn: 222348
* [mips][microMIPS] Implement SDBBP and RDHWR instructions.Jozef Kolek2014-11-194-4/+31
| | | | | | Differential Revision: http://reviews.llvm.org/D5240 llvm-svn: 222347
* [X86][SSE] pslldq/psrldq byte shifts/rotation for SSE2Simon Pilgrim2014-11-192-33/+160
| | | | | | | | | | This patch builds on http://reviews.llvm.org/D5598 to perform byte rotation shuffles (lowerVectorShuffleAsByteRotate) on pre-SSSE3 (palignr) targets - pre-SSSE3 is only enabled on i8 and i16 vector targets where it is a more definite performance gain. I've also added a separate byte shift shuffle (lowerVectorShuffleAsByteShift) that makes use of the ability of the SLLDQ/SRLDQ instructions to implicitly shift in zero bytes to avoid the need to create a zero register if we had used palignr. Differential Revision: http://reviews.llvm.org/D5699 llvm-svn: 222340
* AliasSetTracker: UnknownInsts should contribute to the refcountDavid Majnemer2014-11-191-15/+26
| | | | | | | | | | | | | | | | | | | AliasSetTracker::addUnknown may create an AliasSet devoid of pointers just to contain an instruction if no suitable AliasSet already exists. It will then AliasSet::addUnknownInst and we will be done. However, it's possible for addUnknown to choose an existing AliasSet to addUnknownInst. If this were to occur, we are in a bit of a pickle: removing pointers from the AliasSet can cause the entire AliasSet to become destroyed, taking our unknown instructions out with them. Instead, keep track whether or not our AliasSet has any unknown instructions. This fixes PR21582. llvm-svn: 222338
* Update SetVector to rely on the underlying set's insert to return a ↵David Blaikie2014-11-1997-207/+226
| | | | | | | | | | | | | pair<iterator, bool> This is to be consistent with StringSet and ultimately with the standard library's associative container insert function. This lead to updating SmallSet::insert to return pair<iterator, bool>, and then to update SmallPtrSet::insert to return pair<iterator, bool>, and then to update all the existing users of those functions... llvm-svn: 222334
* [AArch64] Disable useAA for Cortex-A57.Hao Liu2014-11-191-1/+1
| | | | | | | | Using AA during CodeGen is very useful for in-order cores. It is less useful for ooo cores. Also I find enabling useAA for Cortex-A57 may generate worse code for some test cases. If useAA in codegen is improved and benefical for ooo cores, we can enable it again. llvm-svn: 222333
* [AArch64] Enable SeparateConstOffsetFromGEP, EarlyCSE and LICM passes on ↵Hao Liu2014-11-191-0/+18
| | | | | | | | | | | | AArch64 backend. SeparateConstOffsetFromGEP can gives more optimizaiton opportunities related to GEPs, which benefits EarlyCSE and LICM. By enabling these passes we can have better address calculations and generate a better addressing mode. Some SPEC 2006 benchmarks (astar, gobmk, namd) have obvious improvements on Cortex-A57. Reviewed in http://reviews.llvm.org/D5864. llvm-svn: 222331
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