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* Fix broken assert, PR24624Hans Wennborg2016-04-111-1/+1
| | | | llvm-svn: 265989
* Remove redundant .c_str(), as suggested by PR25633Hans Wennborg2016-04-111-1/+1
| | | | llvm-svn: 265988
* Fix a couple of redundant conditional expressions (PR27283, PR28282)Hans Wennborg2016-04-112-3/+3
| | | | llvm-svn: 265987
* use range-loops; NFCISanjay Patel2016-04-111-13/+8
| | | | llvm-svn: 265985
* MCParser: diagnose missing directional labels more clearly.Tim Northover2016-04-111-13/+27
| | | | | | | | Before, ELF at least managed a diagnostic but it was a completely untraceable "undefined symbol" error. MachO had a variety of even worse behaviours: crash, emit corrupt file, or an equally bad message. llvm-svn: 265984
* [LoopUtils, LV] Fix PR27246 (first-order recurrences)Matthew Simpson2016-04-111-1/+1
| | | | | | | | | | | | This patch ensures that when we detect first-order recurrences, we reject a phi node if its previous value is also a phi node. During vectorization the initial and previous values of the recurrence are shuffled together to create the value for the current iteration. However, phi nodes are not widened like other instructions. This fixes PR27246. Differential Revision: http://reviews.llvm.org/D18971 llvm-svn: 265983
* Test commit.Sriraman Tallam2016-04-111-1/+1
| | | | llvm-svn: 265976
* [Object] Make .alt_entry directive parsing MachO specific.Lang Hames2016-04-114-6/+25
| | | | | | ELF and COFF will now treat .alt_entry like any other unrecognized directive. llvm-svn: 265975
* Combine redundant stack realignment booleans in MachineFrameInfoReid Kleckner2016-04-111-17/+14
| | | | | | | | | MachineFrameInfo does not need to be able to distinguish between the user asking us not to realign the stack and the target telling us it doesn't support stack realignment. Either way, fixed stack objects have their alignment clamped. llvm-svn: 265971
* add FIXME comment; NFCSanjay Patel2016-04-111-1/+3
| | | | llvm-svn: 265970
* add an assert for safety; NFCSanjay Patel2016-04-111-0/+2
| | | | llvm-svn: 265969
* variable names start with a capital letter; NFCSanjay Patel2016-04-111-9/+9
| | | | llvm-svn: 265968
* Add code comment/NFCXinliang David Li2016-04-111-0/+4
| | | | llvm-svn: 265966
* [InstCombine] use canEvaluateShiftedShift() to handle the lshr case (NFCI)Sanjay Patel2016-04-111-33/+12
| | | | | | | | | We need just a couple of logic tweaks to consolidate the shl and lshr cases. This is step 5 of refactoring to solve PR26760: https://llvm.org/bugs/show_bug.cgi?id=26760 llvm-svn: 265965
* [InstCombine] don't try to shift an illegal amount (PR26760)Sanjay Patel2016-04-111-1/+3
| | | | | | | | | | This is the straightforward fix for PR26760: https://llvm.org/bugs/show_bug.cgi?id=26760 But we still need to make some changes to generalize this helper function and then send the lshr case into here. llvm-svn: 265960
* TargetRegisterInfo: Add getRegAsmName()Tom Stellard2016-04-111-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: The motivation for this new function is to move an invalid assumption about the relationship between the names of register definitions in tablegen files and their assembly names into TargetRegisterInfo, so that we can begin working on fixing this assumption. The current problem is that if you have a register definition in TableGen like: def MYReg0 : Register<"r0", 0>; The function TargetLowering::getRegForInlineAsmConstraint() derives the assembly name from the tablegen name: "MyReg0" rather than the given assembly name "r0". This is working, because on most targets the tablegen name and the assembly names are case insensitive matches for each other (e.g. def EAX : X86Reg<"eax", ...> getRegAsmName() will allow targets to override this default assumption and return the correct assembly name. Reviewers: echristo, hfinkel Subscribers: SamWot, echristo, hfinkel, llvm-commits Differential Revision: http://reviews.llvm.org/D15614 llvm-svn: 265955
* [InstCombine] rename variables in shifted-shift helper function (NFCI)Sanjay Patel2016-04-111-17/+20
| | | | | | | This is step 3 of refactoring to solve PR26760: https://llvm.org/bugs/show_bug.cgi?id=26760 llvm-svn: 265954
* [InstCombine] add helper function for shift-shift optimization (NFCI)Sanjay Patel2016-04-111-24/+37
| | | | | | | This is step 2 of refactoring to solve PR26760: https://llvm.org/bugs/show_bug.cgi?id=26760 llvm-svn: 265951
* This reverts commit r265913 and r265912Sanjoy Das2016-04-113-217/+5
| | | | | | | | | See PR27315 r265913: "[IndVars] Eliminate op.with.overflow when possible" r265912: "[SCEV] See through op.with.overflow intrinsics" llvm-svn: 265950
* [mips] Make Static a default relocation model for MIPS codegenPetar Jovanovic2016-04-111-3/+1
| | | | | | | | | | | | This change follows up defaults for GCC and Clang, so LLVM does not differ from them. While number of the test files are touched with this change, they all keep the old (expected) behaviour with the explicit option: "-relocation-model=pic" The tests that have not been touched are insensitive to relocation model. Differential Revision: http://reviews.llvm.org/D17995 llvm-svn: 265949
* [mips] Trivial corrections to range checked immediates.Daniel Sanders2016-04-113-9/+8
| | | | | | | | | | | | | | Summary: SYNC has a 5-bit unsigned immediate. Move MIPS16-specific pcrel16 operand to Mips16 files. Reviewers: vkalintiris Subscribers: dsanders, sdardis, llvm-commits Differential Revision: http://reviews.llvm.org/D18755 llvm-svn: 265947
* [ThinLTO] BitcodeWriter still requires Analysis libraryTeresa Johnson2016-04-111-1/+1
| | | | | | | | | | | This should fix bot failure: http://bb.pgr.jp/builders/i686-mingw32-RA-on-linux/builds/9873 The bitcode writer unfortunately still needs the Analysis library, as it replaces old dependence on BFI etc with dependence on new ModuleSummaryAnalysis pass. llvm-svn: 265945
* [SystemZ] README: remove an implemented idea, add some new onesUlrich Weigand2016-04-111-5/+13
| | | | | | | | | | The note about conditional returns can now be removed, as they are implemented. Let's also add 2 new ones in exchange. Author: koriakin Differential Revision: http://reviews.llvm.org/D18962 llvm-svn: 265944
* [SystemZ] Add SVC instructionUlrich Weigand2016-04-112-0/+15
| | | | | | | | | This is going to be useful for inline assembly only. Author: koriakin Differential Revision: http://reviews.llvm.org/D18952 llvm-svn: 265943
* [ThinLTO] Move summary computation from BitcodeWriter to new passTeresa Johnson2016-04-118-161/+268
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: This is the first step in also serializing the index out to LLVM assembly. The per-module summary written to bitcode is moved out of the bitcode writer and to a new analysis pass (ModuleSummaryIndexWrapperPass). The pass itself uses a new builder class to compute index, and the builder class is used directly in places where we don't have a pass manager (e.g. llvm-as). Because we are computing summaries outside of the bitcode writer, we no longer can use value ids created by the bitcode writer's ValueEnumerator. This required changing the reference graph edge type to use a new ValueInfo class holding a union between a GUID (combined index) and Value* (permodule index). The Value* are converted to the appropriate value ID during bitcode writing. Also, this enables removal of the BitWriter library's dependence on the Analysis library that was previously required for the summary computation. Reviewers: joker.eph Subscribers: joker.eph, llvm-commits Differential Revision: http://reviews.llvm.org/D18763 llvm-svn: 265941
* [ARM] Avoid switching ARM/Thumb mode on .arch/.cpu directiveOliver Stannard2016-04-111-0/+30
| | | | | | | | | | | | | | | | | | | | When we see a .arch or .cpu directive, we should try to avoid switching ARM/Thumb mode if possible. If we do have to switch modes, we also need to emit the correct mapping symbol for the new ISA. We did not do this previously, so could emit ARM code with Thumb mapping symbols (or vice-versa). The GAS behaviour is to always stay in the same mode, and to emit an error on any instructions seen when the current mode is not available on the current target. We can't represent that situation easily (we assume that Thumb mode is available if ModeThumb is set), so we differ from the GAS behaviour when switching to a target that can't support the old mode. I've added a warning for when this implicit mode-switch occurs. Differential Revision: http://reviews.llvm.org/D18955 llvm-svn: 265936
* [SystemZ] Support conditional indirect sibling calls via BCRUlrich Weigand2016-04-115-5/+146
| | | | | | | | | | | | | | | This adds a conditional variant of CallBR instruction, CallBCR. Also, it can be fused with integer comparisons, resulting in one of the new C*BCall instructions. In addition to CallBRCL limitations, this has another one: it won't trigger if the function to call isn't already in %r1 - see f22 in the test for an example (it's also why the loads in tests are volatile). Author: koriakin Differential Revision: http://reviews.llvm.org/D18928 llvm-svn: 265933
* [SystemZ] Remove incorrect CC use for C*BReturn instructionsUlrich Weigand2016-04-111-1/+1
| | | | | | | | | These are fused compare-and-branches, so they obviously don't use CC. Author: koriakin Differential Revision: http://reviews.llvm.org/D18927 llvm-svn: 265932
* [X86] Restrict max long nop length for Lakemont.Andrey Turetskiy2016-04-111-1/+2
| | | | | | | | | Restrict the max length of long nops for Lakemont to 7. Experiments on MCU benchmarks (Dhrystone, Coremark) show that this is the most optimal length. Differential Revision: http://reviews.llvm.org/D18897 llvm-svn: 265924
* [IndVars] Eliminate op.with.overflow when possibleSanjoy Das2016-04-101-0/+107
| | | | | | | | | | | | | | | Summary: If we can prove that an op.with.overflow intrinsic does not overflow, we can get rid of the intrinsic, and replace it with non-wrapping arithmetic. Reviewers: atrick, regehr Subscribers: sanjoy, mcrosier, llvm-commits Differential Revision: http://reviews.llvm.org/D18685 llvm-svn: 265913
* [SCEV] See through op.with.overflow intrinsicsSanjoy Das2016-04-102-5/+110
| | | | | | | | | | | | | | | Summary: This change teaches SCEV to see reduce `(extractvalue 0 (op.with.overflow X Y))` into `op X Y` (with a no-wrap tag if possible). Reviewers: atrick, regehr Subscribers: mcrosier, mzolotukhin, llvm-commits Differential Revision: http://reviews.llvm.org/D18684 llvm-svn: 265912
* Plumb the option to emit the `ModuleHash` in the bitcode through the bitcode ↵Mehdi Amini2016-04-101-6/+7
| | | | | | | writer APIs From: Mehdi Amini <mehdi.amini@apple.com> llvm-svn: 265907
* [X86][AVX512BW] Add support for v64i8 multipliesSimon Pilgrim2016-04-101-3/+38
| | | | | | | | | | Extend the existing lowering of vXi8 multiplies to support v64i8 on avx512bw targets. I added the Lower512IntArith helper function to help with this - not sure how often this could be used in the future, but it seemed better than putting all that logic inside LowerMUL. Differential Revision: http://reviews.llvm.org/D18937 llvm-svn: 265902
* Loop vectorization with uniform loadElena Demikhovsky2016-04-101-0/+9
| | | | | | | | | Vectorization cost of uniform load wasn't correctly calculated. As a result, a simple loop that loads a uniform value wasn't vectorized. Differential Revision: http://reviews.llvm.org/D18940 llvm-svn: 265901
* [ThinLTO] Remove unused parameter (NFC)Teresa Johnson2016-04-101-9/+7
| | | | llvm-svn: 265900
* [X86] Use for loops over types to reduce code for setting up operation actions.Craig Topper2016-04-101-150/+97
| | | | llvm-svn: 265893
* [X86] Remove unnecessary setOperationAction for SRA v2i64/v4i64 when VLX is ↵Craig Topper2016-04-101-2/+0
| | | | | | suppored. This is already done for SSE2/AVX2 which VLX implies. NFC llvm-svn: 265892
* [PGO] Fix deserialize bug Xinliang David Li2016-04-101-1/+3
| | | | | | | | | | Raw function pointer collected by value profile data may be from external functions that are not instrumented. They won't have mapping data to be used by the deserializer. Force the value to be 0 in this case. llvm-svn: 265890
* [CodeGen] Don't assume that fixed stack objects are aligned in a ↵Charles Davis2016-04-091-5/+16
| | | | | | | | | | | | | | | | | | | | stack-realigned function. Summary: After we make the adjustment, we can assume that for local allocas, but not for stack parameters, the return address, or any other fixed stack object (which has a negative offset and therefore lies prior to the adjusted SP). Fixes PR26662. Reviewers: hfinkel, qcolombet, rnk Subscribers: rnk, llvm-commits Differential Revision: http://reviews.llvm.org/D18471 llvm-svn: 265886
* [MC] support TLSDESC and TLSCALL / GNU2 tls dialectDavide Italiano2016-04-091-0/+4
| | | | | | Differential Revision: http://reviews.llvm.org/D18885 llvm-svn: 265881
* Drop debug info for DISubprograms that are not referenced by anythingAdrian Prantl2016-04-094-53/+8
| | | | | | | | | | | | | | | | | | | | | This patch drops the debug info for all DISubprograms that are (a) not attached to an llvm::Function and (b) not indirectly reachable via inline scopes from any surviving Function and (c) not reachable from a type (i.e.: member functions). Background: I'm currently working on a patch to reverse the pointers between DICompileUnit and DISubprogram (for more info check Duncan's RFC on lazy-loading of debug info metadata http://lists.llvm.org/pipermail/llvm-dev/2016-March/097419.html). The idea is to remove the list of subprograms from DICompileUnit and instead point to the owning compile unit from each DISubprogram. After doing this all DISubprograms fulfilling the above criteria will be implicitly dropped unless we go through an extra effort to preserve them. http://reviews.llvm.org/D18477 <rdar://problem/25256815> llvm-svn: 265876
* [x86] use BMI 'andn' for logic + compare ops Sanjay Patel2016-04-092-3/+17
| | | | | | | | | | With BMI, we can use 'andn' to save an instruction when the result is only used in a compare. This is related to one of the potential sequences to check 'isfinite' in: https://llvm.org/bugs/show_bug.cgi?id=27164 Differential Revision: http://reviews.llvm.org/D18910 llvm-svn: 265875
* [X86][XOP] Support for VPPERM 2-input shuffle mask decodingSimon Pilgrim2016-04-093-27/+127
| | | | | | | | | | This patch adds support for decoding XOP VPPERM instruction when it represents a basic shuffle. The mask decoding required the existing MCInstrLowering code to be updated to support binary shuffles - the implementation now matches what is done in X86InstrComments.cpp. Differential Revision: http://reviews.llvm.org/D18441 llvm-svn: 265874
* [X86] Use for loops over types to reduce code for setting up operation ↵Craig Topper2016-04-091-149/+78
| | | | | | actions. NFC llvm-svn: 265871
* [X86] Remove calls to setOperationAction that set CTLZ_ZERO_UNDEF for some ↵Craig Topper2016-04-091-16/+0
| | | | | | vector types to Expand. Expand is already set for all operations for all vector types earlier so this is redundant. NFC llvm-svn: 265870
* Maintain calling convention when inling calls to llvm.deoptimizeSanjoy Das2016-04-091-1/+3
| | | | | | | The behavior here was buggy -- we'd forget the calling convention after inlining a callsite calling llvm.deoptimize. llvm-svn: 265867
* [libfuzzer] defensive assertMike Aizatsky2016-04-081-1/+2
| | | | llvm-svn: 265866
* Support the Nodebug emission kind for DICompileUnits.Adrian Prantl2016-04-084-55/+66
| | | | | | | | | | | | | | | | Sample-based profiling and optimization remarks currently remove DICompileUnits from llvm.dbg.cu to suppress the emission of debug info from them. This is somewhat of a hack and only borderline legal IR. This patch uses the recently introduced NoDebug emission kind in DICompileUnit to achieve the same result without breaking the Verifier. A nice side-effect of this change is that it is now possible to combine NoDebug and regular compile units under LTO. http://reviews.llvm.org/D18808 <rdar://problem/25427165> llvm-svn: 265861
* Refactor Threshold computation. NFC.Easwaran Raman2016-04-081-22/+35
| | | | | | This is part of changes reviewed in http://reviews.llvm.org/D17584. llvm-svn: 265852
* [SSP] Remove llvm.stackprotectorcheck.Tim Shen2016-04-0810-132/+109
| | | | | | | | | | This is a cleanup patch for SSP support in LLVM. There is no functional change. llvm.stackprotectorcheck is not needed, because SelectionDAG isn't actually lowering it in SelectBasicBlock; rather, it adds check code in FinishBasicBlock, ignoring the position where the intrinsic is inserted (See FindSplitPointForStackProtector()). llvm-svn: 265851
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