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| author | Daniel Sanders <daniel.sanders@imgtec.com> | 2016-04-11 15:20:40 +0000 |
|---|---|---|
| committer | Daniel Sanders <daniel.sanders@imgtec.com> | 2016-04-11 15:20:40 +0000 |
| commit | a45d3e439f60f993ee4fe7995cc197427bc3c4f6 (patch) | |
| tree | 98d8d65cfbe064edaf87a62cf17eb61078c73ce3 /llvm/lib | |
| parent | 2d2d67994c429c0bf28296b6ae47dee5d7c0951d (diff) | |
| download | bcm5719-llvm-a45d3e439f60f993ee4fe7995cc197427bc3c4f6.tar.gz bcm5719-llvm-a45d3e439f60f993ee4fe7995cc197427bc3c4f6.zip | |
[mips] Trivial corrections to range checked immediates.
Summary:
SYNC has a 5-bit unsigned immediate.
Move MIPS16-specific pcrel16 operand to Mips16 files.
Reviewers: vkalintiris
Subscribers: dsanders, sdardis, llvm-commits
Differential Revision: http://reviews.llvm.org/D18755
llvm-svn: 265947
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/Target/Mips/MicroMips32r6InstrInfo.td | 4 | ||||
| -rw-r--r-- | llvm/lib/Target/Mips/Mips16InstrInfo.td | 2 | ||||
| -rw-r--r-- | llvm/lib/Target/Mips/MipsInstrInfo.td | 11 |
3 files changed, 8 insertions, 9 deletions
diff --git a/llvm/lib/Target/Mips/MicroMips32r6InstrInfo.td b/llvm/lib/Target/Mips/MicroMips32r6InstrInfo.td index 8d1d6685573..b8a40ad6e96 100644 --- a/llvm/lib/Target/Mips/MicroMips32r6InstrInfo.td +++ b/llvm/lib/Target/Mips/MicroMips32r6InstrInfo.td @@ -965,9 +965,9 @@ class LUI_MMR6_DESC : IsAsCheapAsAMove, MMR6Arch<"lui">, MipsR6Inst{ class SYNC_MMR6_DESC : MMR6Arch<"sync">, MipsR6Inst { dag OutOperandList = (outs); - dag InOperandList = (ins i32imm:$stype); + dag InOperandList = (ins uimm5:$stype); string AsmString = !strconcat("sync", "\t$stype"); - list<dag> Pattern = [(MipsSync imm:$stype)]; + list<dag> Pattern = [(MipsSync immZExt5:$stype)]; InstrItinClass Itinerary = NoItinerary; bit HasSideEffects = 1; } diff --git a/llvm/lib/Target/Mips/Mips16InstrInfo.td b/llvm/lib/Target/Mips/Mips16InstrInfo.td index 3b565b0fffb..bd45015700c 100644 --- a/llvm/lib/Target/Mips/Mips16InstrInfo.td +++ b/llvm/lib/Target/Mips/Mips16InstrInfo.td @@ -31,6 +31,8 @@ def mem16_ea : Operand<i32> { let EncoderMethod = "getMemEncoding"; } +def pcrel16 : Operand<i32>; + // // I-type instruction format // diff --git a/llvm/lib/Target/Mips/MipsInstrInfo.td b/llvm/lib/Target/Mips/MipsInstrInfo.td index b426231d776..e9d7f8d43c5 100644 --- a/llvm/lib/Target/Mips/MipsInstrInfo.td +++ b/llvm/lib/Target/Mips/MipsInstrInfo.td @@ -844,10 +844,6 @@ def li16_imm : Operand<i32> { let ParserMatchClass = ConstantUImm7Sub1AsmOperandClass; } - -def pcrel16 : Operand<i32> { -} - def MipsMemAsmOperand : AsmOperandClass { let Name = "Mem"; let ParserMethod = "parseMemOperand"; @@ -1385,8 +1381,8 @@ class DEI_FT<string opstr, RegisterOperand RO> : // Sync let hasSideEffects = 1 in class SYNC_FT<string opstr> : - InstSE<(outs), (ins i32imm:$stype), "sync $stype", [(MipsSync imm:$stype)], - NoItinerary, FrmOther, opstr>; + InstSE<(outs), (ins uimm5:$stype), "sync $stype", + [(MipsSync immZExt5:$stype)], NoItinerary, FrmOther, opstr>; class SYNCI_FT<string opstr> : InstSE<(outs), (ins mem_simm16:$addr), !strconcat(opstr, "\t$addr"), [], @@ -1769,7 +1765,8 @@ let DecoderNamespace = "COP3_" in { } } -def SYNC : MMRel, StdMMR6Rel, SYNC_FT<"sync">, SYNC_FM, ISA_MIPS32; +def SYNC : MMRel, StdMMR6Rel, SYNC_FT<"sync">, SYNC_FM, + ISA_MIPS32; def SYNCI : MMRel, StdMMR6Rel, SYNCI_FT<"synci">, SYNCI_FM, ISA_MIPS32R2; let AdditionalPredicates = [NotInMicroMips] in { |
