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* Debug Info: pass in DIScope instead of DIDescriptor in createMemberType.Manman Ren2013-09-081-1/+1
| | | | | | Improve readability. No functionality change. llvm-svn: 190269
* Add neverHasSideEffects=1 on a couple move instructions.Craig Topper2013-09-082-2/+2
| | | | llvm-svn: 190259
* Using popcount should check the popcount feature flag not the SSE41 feature ↵Craig Topper2013-09-081-2/+2
| | | | | | flag. llvm-svn: 190258
* [mips] Enhance command line option "-mno-ldc1-sdc1" to expand base+index doubleAkira Hatanaka2013-09-076-74/+84
| | | | | | | | | | precision loads and stores as well as reg+imm double precision loads and stores. Previously, expansion of loads and stores was done after register allocation, but now it takes place during legalization. As a result, users will see double precision stores and loads being emitted to spill and restore 64-bit FP registers. llvm-svn: 190235
* [mips] Place parentheses around && to silence warning.Akira Hatanaka2013-09-071-3/+3
| | | | llvm-svn: 190234
* Remove verifier check that attribute 'builtin' is only applied to calls toRichard Smith2013-09-071-8/+0
| | | | | | | | functions marked 'nobuiltin'. That approach doesn't play well with LTO, and there's no harm in marking a call as 'builtin' if it was going to be a builtin regardless. llvm-svn: 190233
* [mips] Add definition of instruction "drotr32" (double rotate right plus 32).Akira Hatanaka2013-09-072-0/+5
| | | | llvm-svn: 190232
* Debug Info: Use identifier to reference DIType in containing type field ofManman Ren2013-09-073-3/+3
| | | | | | | | a DISubprogram. Verifier is updated accordingly. llvm-svn: 190229
* [mips] Use uimm5 and uimm6 instead of shamt and imm, if the immediate has to fitAkira Hatanaka2013-09-076-46/+41
| | | | | | into a 5-bit or 6-bit field. llvm-svn: 190226
* Debug Info: pass in VTableHolder as DIType instead of MDNode *.Manman Ren2013-09-061-5/+5
| | | | | | Remove one cast and improve readability. No functionality change. llvm-svn: 190225
* [mips] Define "trap" as a pseudo instruction that turns into "break 0, 0".Akira Hatanaka2013-09-062-3/+11
| | | | llvm-svn: 190224
* [mips] Delete unused classes and defs.Akira Hatanaka2013-09-061-9/+1
| | | | llvm-svn: 190221
* [mips] Make "b" (unconditional branch) a pseudo. "b" is an assembly idiom, ↵Akira Hatanaka2013-09-064-16/+13
| | | | | | | | which is equivalent to "beq $zero, $zero, offset". llvm-svn: 190220
* [mips] Set instruction itineraries of loads, stores and conditional moves.Akira Hatanaka2013-09-063-33/+35
| | | | llvm-svn: 190219
* TBAA: add isTBAAVtableAccess to MDNode so clients can call the functionManman Ren2013-09-062-6/+21
| | | | | | | | | | | | | instead of having its own implementation. The implementation of isTBAAVtableAccess is in TypeBasedAliasAnalysis.cpp since it is related to the format of TBAA metadata. The path for struct-path tbaa will be exercised by test/Instrumentation/ThreadSanitizer/read_from_global.ll, vptr_read.ll, and vptr_update.ll when struct-path tbaa is on by default. llvm-svn: 190216
* R600: Add support for LDS atomic subtractAaron Watry2013-09-063-0/+13
| | | | | | Signed-off-by: Aaron Watry <awatry@gmail.com> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 190200
* Debug Info: Use identifier to reference DIType in containing type field ofManman Ren2013-09-063-5/+5
| | | | | | | | a DICompositeType. Verifier is updated accordingly. llvm-svn: 190190
* Debug Info: Move a helper function getTypeIdentifier from DIBuilder to be partManman Ren2013-09-062-13/+12
| | | | | | | | | | | of DIType. Implement DIType::generateRef to return a type reference. This function will be used in setContaintingType and in DIBuilder to generete the type reference. No functionality change. llvm-svn: 190188
* mi-sched: cleanup register pressure update, remove a FIXME.Andrew Trick2013-09-061-19/+26
| | | | llvm-svn: 190181
* mi-sched: improve regpressure tracing.Andrew Trick2013-09-061-2/+7
| | | | llvm-svn: 190180
* mi-sched: print tree size in -view-misched-dagsAndrew Trick2013-09-061-1/+5
| | | | llvm-svn: 190179
* mi-sched: register pressure update tracing.Andrew Trick2013-09-061-0/+4
| | | | llvm-svn: 190178
* mi-sched: Reorder Cyclicpath (latency) and CriticalMax (pressure) heuristics.Andrew Trick2013-09-061-4/+4
| | | | | | The latency based scheduling could induce spills in some cases. llvm-svn: 190177
* Added MachineSchedPolicy.Andrew Trick2013-09-061-35/+51
| | | | | | | | Allow subtargets to customize the generic scheduling strategy. This is convenient for targets that don't need to add new heuristics by specializing the strategy. llvm-svn: 190176
* avoid unnecessary direct access to LiveInterval::rangesMatthias Braun2013-09-063-31/+30
| | | | llvm-svn: 190170
* remove unused argument from LiveRanges::join()Matthias Braun2013-09-062-4/+2
| | | | llvm-svn: 190169
* remove pointless assertMatthias Braun2013-09-061-2/+0
| | | | | | The if above it ensures the property anyway. llvm-svn: 190168
* fix commentMatthias Braun2013-09-061-1/+1
| | | | | | There's no 'B3' in the example. llvm-svn: 190167
* [mips][msa] IndentationDaniel Sanders2013-09-061-34/+34
| | | | llvm-svn: 190156
* [mips][msa] Requires<[HasMSA]> is redundant, it is also supplied via inheritanceDaniel Sanders2013-09-061-628/+628
| | | | | | | Tested with 'llvm-tblgen -print-records' which outputs identical records before and after this patch. llvm-svn: 190155
* This patch adds support for microMIPS Multiply and Add/Sub instructions. ↵Vladimir Medic2013-09-062-5/+11
| | | | | | Test cases are included in patch. llvm-svn: 190154
* [mips][msa] Made the operand register sets optional for the VEC formatsDaniel Sanders2013-09-061-16/+9
| | | | | | | | Their default is to be the same as the result register set. No functional change llvm-svn: 190153
* This patch adds support for microMIPS Move to/from HI/LO instructions. Test ↵Vladimir Medic2013-09-064-8/+44
| | | | | | cases are included in patch. llvm-svn: 190152
* [mips][msa] Made the operand register sets optional for the ELM_INSVE formatsDaniel Sanders2013-09-061-14/+10
| | | | | | | | Their default is to be the same as the result register set. No functional change llvm-svn: 190151
* [mips][msa] Made the operand register sets optional for the 3RF_4RF formatDaniel Sanders2013-09-061-14/+14
| | | | | | | | Their default is to be the same as the result register set. No functional change llvm-svn: 190150
* This patch adds support for microMIPS Move Conditional instructions. Test ↵Vladimir Medic2013-09-064-8/+33
| | | | | | cases are included in patch. llvm-svn: 190148
* SelectionDAG: create correct BooleanContent constantsTim Northover2013-09-062-2/+11
| | | | | | | | | | | | | | | Occasionally DAGCombiner can spot that a SETCC operation is completely redundant and reduce it to "all true" or "all false". If this happens to a vector, the value produced has to take account of what a normal comparison would have produced, which may be an all-1s bitmask. The fix in SelectionDAG.cpp is tested, however, as far as I can see the code in TargetLowering.cpp is possibly unreachable and almost certainly irrelevant when triggered so there are no tests. However, I believe it's still clearly the right change and may save someone else some hassle if it suddenly becomes reachable. So I'm doing it anyway. llvm-svn: 190147
* [mips][msa] Made the operand register sets optional for the 3RF formatsDaniel Sanders2013-09-061-132/+72
| | | | | | | | Their default is to be the same as the result register set. No functional change llvm-svn: 190146
* [mips][msa] Made the operand register sets optional for the 3R_4R formatDaniel Sanders2013-09-061-30/+22
| | | | | | | | Their default is to be the same as the result register set. No functional change llvm-svn: 190145
* This patch adds support for microMIPS disassembler and disassembler make ↵Vladimir Medic2013-09-062-17/+93
| | | | | | check tests. llvm-svn: 190144
* [mips][msa] Made the operand register sets optional for the 2RF formatDaniel Sanders2013-09-061-59/+39
| | | | | | | | Their default is to be the same as the result register set. No functional change llvm-svn: 190143
* [mips][msa] Made the operand register sets optional for the I8 formatDaniel Sanders2013-09-061-21/+12
| | | | | | | | Their default is to be the same as the result register set. No functional change llvm-svn: 190142
* [mips][msa] Made the operand register sets optional for the I5 and SI5 formatsDaniel Sanders2013-09-061-74/+46
| | | | | | | | Their default is to be the same as the result register set. No functional change llvm-svn: 190141
* [mips][msa] Made the operand register sets optional for the BIT_[BHWD] formatsDaniel Sanders2013-09-061-104/+60
| | | | | | | | Their default is to be the same as the result register set. No functional change llvm-svn: 190140
* [SystemZ] Tweak integer comparison codeRichard Sandiford2013-09-066-121/+122
| | | | | | | | | | | | | | | | | | | The architecture has many comparison instructions, including some that extend one of the operands. The signed comparison instructions use sign extensions and the unsigned comparison instructions use zero extensions. In cases where we had a free choice between signed or unsigned comparisons, we were trying to decide at lowering time which would best fit the available instructions, taking things like extension type into account. The code to do that was getting increasingly hairy and was also making some bad decisions. E.g. when comparing the result of two LLCs, it is better to use CR rather than CLR, since CR can be fused with a branch while CLR can't. This patch removes the lowering code and instead adds an operand to integer comparisons to say whether signed comparison is required, whether unsigned comparison is required, or whether either is OK. We can then leave the choice of instruction up to the normal isel code. llvm-svn: 190138
* [mips][msa] Sorted MSA_BIT_[BHWD]_DESC_BASE into ascending order of element sizeDaniel Sanders2013-09-061-16/+16
| | | | | | No functional change llvm-svn: 190134
* [mips][msa] Made the operand register sets optional for the 3R formatDaniel Sanders2013-09-061-460/+280
| | | | | | | | Their default is to be the same as the result register set. No functional change llvm-svn: 190133
* [mips][msa] Made the InstrItinClass argument optional since it is always ↵Daniel Sanders2013-09-061-600/+607
| | | | | | | | NoItinerary at the moment. No functional change llvm-svn: 190131
* [SystemZ] Use XC for a memset of 0Richard Sandiford2013-09-061-8/+21
| | | | llvm-svn: 190130
* Use type helper functions.Matt Arsenault2013-09-063-4/+3
| | | | llvm-svn: 190113
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