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* [AVX512] VPERMQ/VPERMPD/VPERMIL single op shuffles are not variable shufflesSimon Pilgrim2018-04-241-4/+5
| | | | | | These variants all take an immediate shuffle mask value and should be scheduled as such. llvm-svn: 330747
* Let TableGen write output only if it changed, instead of doing so in cmake.Nico Weber2018-04-241-5/+16
| | | | | | | | | | | Removes one subprocess and one temp file from the build for each tablegen invocation. No intended behavior change. https://reviews.llvm.org/D45899 llvm-svn: 330742
* Reland "[mips] Guard traps for microMIPS correctly"Simon Dardis2018-04-242-28/+39
| | | | | | | | | | | | | | This is part of fixing the instruction predicates for MIPS. Reviewers: atanasyan, abeserminji Differential Revision: https://reviews.llvm.org/D44212 This patch relands r327409, hopefully without the problematic part of the tests that cause FileCheck to assert on the windows expensive checks bot. llvm-svn: 330741
* [LV][VPlan] Detect outer loops for explicit vectorization.Diego Caballero2018-04-242-29/+394
| | | | | | | | | | | | | | | | | Patch #2 from VPlan Outer Loop Vectorization Patch Series #1 (RFC: http://lists.llvm.org/pipermail/llvm-dev/2017-December/119523.html). This patch introduces the basic infrastructure to detect, legality check and process outer loops annotated with hints for explicit vectorization. All these changes are protected under the feature flag -enable-vplan-native-path. This should make this patch NFC for the existing inner loop vectorizer. Reviewers: hfinkel, mkuper, rengolin, fhahn, aemerson, mssimpso. Differential Revision: https://reviews.llvm.org/D42447 llvm-svn: 330739
* [LoopInterchange] Make isProfitableForVectorization slightly more conservative.Florian Hahn2018-04-241-1/+2
| | | | | | | | | | | | | | | | After D43236, we started interchanging loops with empty dependence matrices. In isProfitableForVectorization, we try to determine if interchanging makes the loop dependences more friendly to the vectorizer. If there are no dependences, we should not interchange, based on that heuristic. Reviewers: efriedma, mcrosier, karthikthecool, blitz.opensource Reviewed By: mcrosier Differential Revision: https://reviews.llvm.org/D45208 llvm-svn: 330738
* [X86][F16C] Add WriteCvtF2FSt scheduling classSimon Pilgrim2018-04-2412-48/+46
| | | | | | Fixes the classification of VCVTPS2PHmr/VCVTPS2PHYmr which were tagged as WriteCvtF2FLd_WriteRMW (PR36887) llvm-svn: 330737
* [X86][BtVer2] Fix VCVTPS2PHmr/VCVTPS2PHYmr latenciesSimon Pilgrim2018-04-241-2/+2
| | | | | | These are stores, not loads, so don't need to account for load latency. llvm-svn: 330735
* [mips] Show an error if register number is out of rangeSimon Atanasyan2018-04-241-1/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Current code does not check that a register number is in the 0-31 range. Sometimes the parser checks that later for some kinds of instructions, but that leads to unclear / incorrect error messages like that: % cat test.s .text lb $4, 8($32) % llvm-mc test.s -triple=mips64-unknown-linux test.s:2:10: error: expected memory with 16-bit signed offset lb $4, 8($32) ^ Sometimes the parser just crashes: % cat test.s .text lw $4, 8($32) % llvm-mc test.s -triple=mips64-unknown-linux This patch resolves the problem by checking that register number after '$' sign is in the 0-31 range. If the number is out of the range the parser shows the `invalid register number` error, but treats invalid register number as a normal one to continue parsing and catch other possible errors. Differential Revision: https://reviews.llvm.org/D45919 llvm-svn: 330732
* [AMDGPU][Waitcnt] NFC. Cleanup some code/naming consistency:Mark Searles2018-04-241-38/+38
| | | | | | - s/SWaitcnt/Waitcnt s/WaitCnt/Waitcnt llvm-svn: 330730
* Fix some layering in AggressiveInstCombine (avoiding inclusion of Scalar.h)David Blaikie2018-04-243-5/+6
| | | | llvm-svn: 330726
* [LoadStoreVectorize] Ignore interleaved invariant loads.Benjamin Kramer2018-04-241-5/+13
| | | | | | | | | The memory location an invariant load is using can never be clobbered by any store, so it's safe to move the load ahead of the store. Differential Revision: https://reviews.llvm.org/D46011 llvm-svn: 330725
* [X86] Remove unnecessary FMA reg-mem InstRW scheduler overrides.Simon Pilgrim2018-04-244-15/+1
| | | | llvm-svn: 330720
* [SystemZ] Use preferred 16-byte function alignmentUlrich Weigand2018-04-241-0/+2
| | | | | | | | While not necessary for correctness, it is preferable for performance reasons on all architectures we currently support to align functions to 16-byte boundaries by default. llvm-svn: 330718
* [X86] Add vector element insertion/extraction scheduler classesSimon Pilgrim2018-04-2413-244/+184
| | | | | | | | | | | | Split off pinsr/pextr and extractps instructions. (Mostly) fixes PR36887. Note: It might be worth adding a WriteFInsertLd class as well in the future. Differential Revision: https://reviews.llvm.org/D45929 llvm-svn: 330714
* [X86] Replace action Promote with Expand for operation ISD::SINT_TO_FPAlexander Ivchenko2018-04-241-1/+3
| | | | | | | | | | | | | | | | | | | | | | | Summary: If attribute "use-soft-float"="true" is set then X86ISelLowering.cpp sets 'Promote' action for ISD::SINT_TO_FP operation on type i32. But 'Promote' action is not proper in this case since lib function __floatsidf is available for casting from signed int to float type. Thus Expand action is more suitable here. The Expand action should be set for ISD::UINT_TO_FP for soft float as well. If function attribute "use-soft-float"="true" is set then infinite looping can happen in DAG combining, function visitSINT_TO_FP() replaces SINT_TO_FP node with UINT_TO_FP node and function combineUIntToFP() replace vice versa in cycle. The fix prevents it. Patch by vrybalov Differential Revision: https://reviews.llvm.org/D45572 llvm-svn: 330711
* [CodeGen] Print user-friendly debug locations as MI commentsFrancis Visoiu Mistrih2018-04-241-1/+14
| | | | | | | | | | | | If available, print the file, line and column of the DebugLoc attached to the MachineInstr: MOV16mr $rbp, 1, $noreg, -112, $noreg, killed renamable $ax, debug-location !56 :: (store 2 into %ir.._value12); stepping.swift:10:17 renamable $edx = MOVZX32rm16 $rbp, 1, $noreg, -112, $noreg, debug-location !62 :: (dereferenceable load 2 from %ir.._value13); stepping.swift:10:17 Differential Revision: https://reviews.llvm.org/D45992 llvm-svn: 330709
* [PM/LoopUnswitch] Fix a bug in the loop block set formation of the newChandler Carruth2018-04-241-4/+10
| | | | | | | | | | | | | | | | | | loop unswitch. This code incorrectly added the header to the loop block set early. As a consequence we would incorrectly conclude that a nested loop body had already been visited when the header of the outer loop was the preheader of the nested loop. In retrospect, adding the header eagerly doesn't really make sense. It seems nicer to let the cycle be formed naturally. This will catch crazy bugs in the CFG reconstruction where we can't correctly form the cycle earlier rather than later, and makes the rest of the logic just fall out. I've also added various asserts that make these issues *much* easier to debug. llvm-svn: 330707
* Correct dwarf unwind information in function epiloguePetar Jovanovic2018-04-248-33/+446
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch aims to provide correct dwarf unwind information in function epilogue for X86. It consists of two parts. The first part inserts CFI instructions that set appropriate cfa offset and cfa register in emitEpilogue() in X86FrameLowering. This part is X86 specific. The second part is platform independent and ensures that: * CFI instructions do not affect code generation (they are not counted as instructions when tail duplicating or tail merging) * Unwind information remains correct when a function is modified by different passes. This is done in a late pass by analyzing information about cfa offset and cfa register in BBs and inserting additional CFI directives where necessary. Added CFIInstrInserter pass: * analyzes each basic block to determine cfa offset and register are valid at its entry and exit * verifies that outgoing cfa offset and register of predecessor blocks match incoming values of their successors * inserts additional CFI directives at basic block beginning to correct the rule for calculating CFA Having CFI instructions in function epilogue can cause incorrect CFA calculation rule for some basic blocks. This can happen if, due to basic block reordering, or the existence of multiple epilogue blocks, some of the blocks have wrong cfa offset and register values set by the epilogue block above them. CFIInstrInserter is currently run only on X86, but can be used by any target that implements support for adding CFI instructions in epilogue. Patch by Violeta Vukobrat. Differential Revision: https://reviews.llvm.org/D42848 llvm-svn: 330706
* [mips] Correct the patterns for bswapSimon Dardis2018-04-243-4/+7
| | | | | | | | | | | | | | Guard the MIPS64 variant correctly for i64, mark the MIPS32 version as not in microMIPS and provide the microMIPS version. Additionally, remove a related stale XFAIL'd test as bswap has its own test case providing coverage. Reviewers: smaksimovic, abeserminji, atanasyan Differential Revision: https://reviews.llvm.org/D45816 llvm-svn: 330705
* [CodeGen] Do not allow opt-bisect-limit to skip ScalarizeMaskedMemIntrin.Andrei Elovikov2018-04-241-3/+0
| | | | | | | | | | | | | | | | | Summary: The pass is supposed to scalarize such intrinsics if the target does not support them natively, so if the scalarization does not happen instruction selection crashes due to inability to lower these intrinsics. Reviewers: andrew.w.kaylor, craig.topper Reviewed By: andrew.w.kaylor Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D45947 llvm-svn: 330700
* [NFC] Remove recently added SE verification because it may be false-positiveMax Kazantsev2018-04-242-12/+0
| | | | llvm-svn: 330699
* [AArch64][SVE] Asm: Support for contiguous, first-faulting LDFF1 ↵Sander de Smalen2018-04-242-1/+33
| | | | | | | | | | | | | | (scalar+scalar) load instructions. Reviewers: fhahn, rengolin, samparker, SjoerdMeijer, t.p.northover, echristo, evandro, javed.absar Reviewed By: rengolin Subscribers: tschuett, kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D45946 llvm-svn: 330697
* [LVI] Fix typo. NFCXin Tong2018-04-241-1/+1
| | | | llvm-svn: 330688
* [NFC] Use forgetTopmostLoop instead of logic duplicationMax Kazantsev2018-04-241-6/+2
| | | | llvm-svn: 330683
* [X86] Add a BSWAP16 instruction using the 32-bit encoding plus a 0x66 prefix.Craig Topper2018-04-241-2/+6
| | | | | | This encoding is recognized by the CPU, but the behavior is undefined. This makes the disassembler handle it correctly so we don't print bswapl with a 16-bit register. llvm-svn: 330682
* [PM/LoopUnswitch] Remove another over-aggressive assert.Chandler Carruth2018-04-241-4/+1
| | | | | | | | | | This code path can very clearly be called in a context where we have baselined all the cloned blocks to a particular loop and are trying to handle nested subloops. There is no harm in this, so just relax the assert. I've added a test case that will make sure we actually exercise this code path. llvm-svn: 330680
* Remove unused function HexagonEarlyIfConversion::replacePhiEdges. NFC.Eric Christopher2018-04-241-15/+0
| | | | llvm-svn: 330678
* [NFC] Add clarification commentMax Kazantsev2018-04-241-2/+4
| | | | llvm-svn: 330677
* Reflow formatting after previous NFC commit.Eric Christopher2018-04-241-6/+6
| | | | llvm-svn: 330676
* Change if-conditionals to else-if as they should all be mutually exclusive.Eric Christopher2018-04-241-3/+3
| | | | | | No functional change intended. llvm-svn: 330675
* InstCombine: Fix layering by not including Scalar.h in InstCombineDavid Blaikie2018-04-243-5/+7
| | | | | | | | (notionally Scalar.h is part of libLLVMScalarOpts, so it shouldn't be included by InstCombine which doesn't/shouldn't need to depend on ScalarOpts) llvm-svn: 330669
* [AggressiveInstCombine] Add aggressive inst combiner to the LLVM C API.Craig Topper2018-04-242-0/+8
| | | | | | I just tried to copy what was done for regular InstCombine. Hopefully I didn't miss anything. llvm-svn: 330668
* Reland r301880(!): "[InstSimplify] Handle selects of GEPs with 0 offset"George Burgess IV2018-04-241-0/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | I was reminded today that this patch got reverted in r301885. I can no longer reproduce the failure that caused the revert locally (...almost one year later), and the patch applied pretty cleanly, so I guess we'll see if the bots still get angry about it. The original breakage was InstSimplify complaining (in "assertion failed" form) about getting passed some crazy IR when running `ninja check-sanitizer`. I'm unable to find traces of what, exactly, said crazy IR was. I suppose we'll find out pretty soon if that's still the case. :) Original commit: Author: gbiv Date: Mon May 1 18:12:08 2017 New Revision: 301880 URL: http://llvm.org/viewvc/llvm-project?rev=301880&view=rev Log: [InstSimplify] Handle selects of GEPs with 0 offset In particular (since it wouldn't fit nicely in the summary): (select (icmp eq V 0) P (getelementptr P V)) -> (getelementptr P V) Differential Revision: https://reviews.llvm.org/D31435 llvm-svn: 330667
* [HWASan] Use dynamic shadow memory on Android only (LLVM)Alex Shlyapnikov2018-04-241-4/+2
| | | | | | | | There're issues with IFUNC support on other platforms. DIfferential Revision: https://reviews.llvm.org/D45840 llvm-svn: 330665
* [AggressiveInstCombine] Add library initializer routine for ↵Craig Topper2018-04-241-0/+5
| | | | | | | | AggressiveInstCombine library. Use it in bugpoint and llvm-opt-fuzzer to match regular InstCombine. This should make aggressive instcombine usable with these tools. llvm-svn: 330663
* [X86] Remove unnecessary vector memory folded InstRW overrides.Simon Pilgrim2018-04-234-187/+4
| | | | | | We have test coverage for these with resources-sse*/avx* llvm-svn: 330662
* [LLVM-C] DIBuilder Bindings For Variable ExpressionsRobert Widmann2018-04-231-0/+66
| | | | | | | | | | | | | | Summary: Add DIBuilder bindings for (global) variable expressions, variable value expressions, and debug value intrinsic insertion. Reviewers: harlanhaskins, deadalnix, whitequark Reviewed By: whitequark Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D45979 llvm-svn: 330661
* [X86] Remove unnecessary BMI2 InstRW overrides.Simon Pilgrim2018-04-233-30/+6
| | | | | | We have test coverage for these with resources-bmi2.s llvm-svn: 330659
* [LoopInterchange] Do not change LI for BBs in child loops.Florian Hahn2018-04-231-0/+3
| | | | | | | | | | | | | | If a loop with child loops becomes our new inner loop after interchanging, we only need to update LoopInfo for the blocks defined in the old outer loop. BBs in child loops will stay there. Reviewers: efriedma, karthikthecool, mcrosier Reviewed By: efriedma Differential Revision: https://reviews.llvm.org/D45970 llvm-svn: 330653
* [X86] Remove unnecessary WriteLEA InstRW overrides.Simon Pilgrim2018-04-235-16/+5
| | | | llvm-svn: 330648
* [DAGCombiner] Unfold scalar masked merge if profitableRoman Lebedev2018-04-231-0/+67
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: This is [[ https://bugs.llvm.org/show_bug.cgi?id=37104 | PR37104 ]]. [[ https://bugs.llvm.org/show_bug.cgi?id=6773 | PR6773 ]] will introduce an IR canonicalization that is likely bad for the end assembly. Previously, `andl`+`andn`/`andps`+`andnps` / `bic`/`bsl` would be generated. (see `@out`) Now, they would no longer be generated (see `@in`). So we need to make sure that they are still generated. If the mask is constant, we do nothing. InstCombine should have unfolded it. Else, i use `hasAndNot()` TLI hook. For now, only handle scalars. https://rise4fun.com/Alive/bO6 ---- I *really* don't like the code i wrote in `DAGCombiner::unfoldMaskedMerge()`. It is super fragile. Is there something like IR Pattern Matchers for this? Reviewers: spatel, craig.topper, RKSimon, javed.absar Reviewed By: spatel Subscribers: andreadb, courbet, kristof.beyls, javed.absar, rengolin, nemanjai, llvm-commits Differential Revision: https://reviews.llvm.org/D45733 llvm-svn: 330646
* [CallSiteSplit] Make sure we remove nonnull if the parameter turns out to be ↵Xin Tong2018-04-231-1/+5
| | | | | | | | | | | | | | a constant. Summary: We do not need nonull attribute if we know an argument is going to be constant. Reviewers: junbuml, davide, fhahn Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D45608 llvm-svn: 330641
* [X86] Revert r330638 - accidental commitGabor Buella2018-04-237-62/+2
| | | | llvm-svn: 330640
* [X86] movdiri and movdir64b instructionsGabor Buella2018-04-237-2/+62
| | | | | Reviewers: craig.topper llvm-svn: 330638
* [MemCpyOpt] Skip optimizing basic blocks not reachable from entryBjorn Pettersson2018-04-231-1/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: Skip basic blocks not reachable from the entry node in MemCpyOptPass::iterateOnFunction. Code that is unreachable may have properties that do not exist for reachable code (an instruction in a basic block can for example be dominated by a later instruction in the same basic block, for example if there is a single block loop). MemCpyOptPass::processStore is only safe to use for reachable basic blocks, since it may iterate past the basic block beginning when used for unreachable blocks. By simply skipping to optimize unreachable basic blocks we can avoid asserts such as "Assertion `!NodePtr->isKnownSentinel()' failed." in MemCpyOptPass::processStore. The problem was detected by fuzz tests. Reviewers: eli.friedman, dneilson, efriedma Reviewed By: efriedma Subscribers: efriedma, llvm-commits Differential Revision: https://reviews.llvm.org/D45889 llvm-svn: 330635
* [WebAssembly] MC: Refactor section creation codeSam Clegg2018-04-231-17/+14
| | | | | | | | | Remove the use of default argument in favor of a separate startCustomSection method. Differential Revision: https://reviews.llvm.org/D45794 llvm-svn: 330632
* Reland r329956, "AArch64: Introduce a DAG combine for folding offsets into ↵Peter Collingbourne2018-04-232-15/+74
| | | | | | | | | | | | | | | | | | | | addresses.", with a fix for the bot failure. This reland includes a check to prevent the DAG combiner from folding an offset that is smaller than the existing one. This can cause oscillations between two possible DAGs, which was the cause of the hang and later assertion failure observed on the lnt-ctmark-aarch64-O3-flto bot. http://green.lab.llvm.org/green/job/lnt-ctmark-aarch64-O3-flto/2024/ Original commit message: > This is a code size win in code that takes offseted addresses > frequently, such as C++ constructors that typically need to compute > an offseted address of a vtable. This reduces the size of Chromium > for Android's .text section by 108KB. Differential Revision: https://reviews.llvm.org/D45199 llvm-svn: 330630
* [DSE] Teach the pass that atomic memory intrinsics are stores.Daniel Neilson2018-04-232-9/+32
| | | | | | | | | | | | | | | | | | | Summary: This change teaches DSE that the atomic memory intrinsics are stores that can be eliminated, and can allow other stores to be eliminated. This change specifically does not teach DSE that these intrinsics can be partially eliminated (i.e. length reduced, and dest/src changed); that will be handled in another change. Reviewers: mkazantsev, skatkov, apilipenko, efriedma, rsmith Reviewed By: efriedma Subscribers: dmgreen, llvm-commits Differential Revision: https://reviews.llvm.org/D45535 llvm-svn: 330629
* [HWASan] Switch back to fixed shadow mapping for x86-64Alex Shlyapnikov2018-04-231-1/+1
| | | | | | | | | | For now switch back to fixed shadow mapping for x86-64 due to the issues with IFUNC linking on older binutils. More details will be added to https://bugs.chromium.org/p/chromium/issues/detail?id=835864 Differential Revision: https://reviews.llvm.org/D45840 llvm-svn: 330623
* [SelectionDAG] Dump debug locs in SDNodesVedant Kumar2018-04-231-0/+4
| | | | | | | | | This helps debug issues where selection-dag assigns the wrong location to an instruction. Differential Revision: https://reviews.llvm.org/D45913 llvm-svn: 330618
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