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* [X86] Add support for "probe-stack" attributewhitequark2017-06-223-19/+37
| | | | | | | | | | | This commit adds prologue code emission for stack probe function calls. Reviewed By: majnemer Differential Revision: https://reviews.llvm.org/D34387 llvm-svn: 306010
* [ARM] Create relocations for beq.w branches to ARM function syms.Florian Hahn2017-06-221-0/+1
| | | | | | | | | | | | | | | | | | Summary: The ARM ELF ABI requires the linker to do interworking for wide conditional branches from Thumb code to ARM code. That was pointed out by @peter.smith in the comments for D33436. Reviewers: rafael, peter.smith, echristo Reviewed By: peter.smith Subscribers: aemerson, javed.absar, kristof.beyls, llvm-commits, peter.smith Differential Revision: https://reviews.llvm.org/D34447 llvm-svn: 306009
* [InstCombine] add peekThroughBitcast() helper; NFCSanjay Patel2017-06-222-6/+14
| | | | | | This is an NFC portion of D33517. We have similar helpers in the backend. llvm-svn: 306008
* [mips] Allow $AT to be used as a register namePetar Jovanovic2017-06-221-1/+1
| | | | | | | | | | | This patch allows $AT to be used as a register name in assembly files. Currently only $at is recognized as a valid register name. Patch by Stanislav Ocovaj. Differential Revision: https://reviews.llvm.org/D34348 llvm-svn: 306007
* [DAG] Add Target Store Merge pass ordering functionNirav Dave2017-06-221-1/+2
| | | | | | | Allow targets to specify if they should merge stores before or after legalization. llvm-svn: 306006
* Revert "[Support] Add RetryAfterSignal helper function" and subsequent fixPavel Labath2017-06-223-12/+25
| | | | | | | | | | | The fix in r306003 uncovered a pretty fundamental problem that libc++ implementation of std::result_of does not handle the prototype of open(2) correctly (presumably because it contains ...). This makes the whole function unusable in its current form, so I am also reverting the original commit (r305892), which introduced the function, at least until I figure out a way to solve the libc++ issue. llvm-svn: 306005
* [Hexagon] Recognize potential offset overflow for store-imm to stackKrzysztof Parzyszek2017-06-221-4/+39
| | | | | | | Reserve an extra scavenging stack slot if the offset field in store- -immediate instructions may overflow. llvm-svn: 306004
* Revert [mips] Adds support for R_MIPS_26, HIGHER, HIGHEST relocations in ↵Sagar Thakur2017-06-224-124/+15
| | | | | | | | RuntimeDyld Reverting due to build bot failures llvm-svn: 306000
* [AMDGPU] SDWA: remove support for VOP2 instructions that have only 64-bit ↵Sam Kolton2017-06-221-11/+15
| | | | | | | | | | | | | | | | encoding Summary: Despite that this instructions are listed in VOP2, they are treated as VOP3 in specs. They should not support SDWA. There are no real instructions for them, but there are pseudo instructions. Reviewers: arsenm, vpykhtin, cfang Subscribers: kzhuravl, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye Differential Revision: https://reviews.llvm.org/D34403 llvm-svn: 305999
* Don't conditionalize Neon instructions, even in IT blocks.Kristof Beyls2017-06-221-3/+5
| | | | | | | | | | | | | | This has been deprecated since ARMARM v7-AR, release C.b, published back in 2012. This also removes test/CodeGen/Thumb2/ifcvt-neon.ll that originally was introduced to check that conditionalization of Neon instructions did happen when generating Thumb2. However, the test had evolved and was no longer testing that. Rather than trying to adapt that test, this commit introduces test/CodeGen/Thumb2/ifcvt-neon-deprecated.mir, since we can now use the MIR framework to write nicer/more maintainable tests. llvm-svn: 305998
* [mips] Adds support for R_MIPS_26, HIGHER, HIGHEST relocations in RuntimeDyldSagar Thakur2017-06-224-15/+124
| | | | | | | | | After the N64 static relocation model support was added to llvm it is required to add its support in RuntimeDyld also because lldb uses ExecutionEngine for evaluating expressions. Reviewed by sdardis Differential: D31649 llvm-svn: 305997
* [mips] Implement the ".rdata" MIPS assembly directive.Simon Dardis2017-06-221-0/+22
| | | | | | | | | | | | | | Rather than creating a separate ".rdata" section distinct from the customary ".rodata" in ELF, ".rdata" switches to the ".rodata" section. This patch relands r305949 and r305950 with the correct commit message and addresses nit raised during review. Patch By: John Baldwin! Differential Revision: https://reviews.llvm.org/D34452 llvm-svn: 305995
* [ARM] Add .w aliases of MOV with shifted operandJohn Brawn2017-06-222-2/+14
| | | | | | | | These appear to have been simply missing. Differential Revision: https://reviews.llvm.org/D34461 llvm-svn: 305993
* [ARM] Clean up choice of narrow instructions in ARMAsmParser, NFCJohn Brawn2017-06-221-33/+27
| | | | | | | | | | | This patch makes a couple of changes to how we decide whether to use the narrow or wide encoding of thumb2 instructions: * Common out the detection of the .w qualifier * Check for the CPSR operand in a consistent way Differential Revision: https://reviews.llvm.org/D34460 llvm-svn: 305992
* Revert "Enable vectorizer-maximize-bandwidth by default."Diana Picus2017-06-221-1/+1
| | | | | | This reverts commit r305960 because it broke self-hosting on AArch64. llvm-svn: 305990
* [GlobalISel][X86] Support vector type G_INSERT legalization/selection.Igor Breger2017-06-222-3/+136
| | | | | | | | | | | | | | | | Summary: Support vector type G_INSERT legalization/selection. Split from https://reviews.llvm.org/D33665 Reviewers: qcolombet, t.p.northover, zvi, guyblank Reviewed By: guyblank Subscribers: guyblank, rovka, llvm-commits, kristof.beyls Differential Revision: https://reviews.llvm.org/D33956 llvm-svn: 305989
* [ARM] Add macro fusion for AES instructions.Florian Hahn2017-06-226-1/+99
| | | | | | | | | | | | | | | | Summary: This patch adds a macro fusion using CodeGen/MacroFusion.cpp to pair AES instructions back to back and adds FeatureFuseAES to enable the feature. Reviewers: evandro, javed.absar, rengolin, t.p.northover Reviewed By: javed.absar Subscribers: aemerson, mgorny, kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D34142 llvm-svn: 305988
* AVX-512: Lowering Masked Gather intrinsic - fixed a bugElena Demikhovsky2017-06-225-9/+103
| | | | | | | | | | | | Masked gather for vector length 2 is lowered incorrectly for element type i32. The type <2 x i32> was automatically extended to <2 x i64> and we generated VPGATHERQQ instead of VPGATHERQD. The type <2 x float> is extended to <4 x float>, so there is no bug for this type, but the sequence may be more optimal. In this patch I'm fixing <2 x i32>bug and optimizing <2 x float> sequence for GATHERs only. The same fix should be done for Scatters as well. Differential revision: https://reviews.llvm.org/D34343 llvm-svn: 305987
* [AMDGPU] SDWA: add support for GFX9 in peephole passSam Kolton2017-06-226-39/+127
| | | | | | | | | | | | | | | | Summary: Added support based on merged SDWA pseudo instructions. Now peephole allow one scalar operand, omod and clamp modifiers. Added several subtarget features for GFX9 SDWA. This diff also contains changes from D34026. Depends D34026 Reviewers: vpykhtin, rampitec, arsenm Subscribers: kzhuravl, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye Differential Revision: https://reviews.llvm.org/D34241 llvm-svn: 305986
* [PowerPC] fix potential verification errorsHiroshi Inoue2017-06-222-5/+12
| | | | | | This patch fixes trivial mishandling of 32-bit/64-bit instructions that may cause verification errors with -verify-machineinstrs. llvm-svn: 305984
* [llvm-readobj] Dump the COFF image load configReid Kleckner2017-06-221-0/+20
| | | | | | | | This includes the safe SEH tables and the control flow guard function table. LLD will emit the guard table soon, and I need a tool that dumps them for testing. llvm-svn: 305979
* [wasm] Fix WebAssembly asm backend after r305968Reid Kleckner2017-06-221-10/+12
| | | | llvm-svn: 305978
* Revert "[Target] Implement the ".rdata" MIPS assembly directive."Davide Italiano2017-06-221-22/+0
| | | | | | | This reverts commit r305949 and r305950 as they didn't have the correct commit message. llvm-svn: 305973
* [WebAssembly] Cleanup WasmObjectWriter.cpp. NFCSam Clegg2017-06-211-78/+70
| | | | | | | | | | | - Use auto where appropriate - Use early return to reduce nesting - Remove stray comment line - Use C++ foreach over explicit iterator Differential Revision: https://reviews.llvm.org/D34477 llvm-svn: 305971
* [AMDGPU] Add FP_CLASS to the add/setcc combineStanislav Mekhanoshin2017-06-211-1/+3
| | | | | | | | This is one of the nodes which also compile as v_cmp_*. Differential Revision: https://reviews.llvm.org/D34485 llvm-svn: 305970
* [ProfileData, Support] Fix some Clang-tidy modernize-use-using and Include ↵Eugene Zelenko2017-06-217-60/+92
| | | | | | What You Use warnings; other minor fixes (NFC). llvm-svn: 305969
* Use a MutableArrayRef. NFC.Rafael Espindola2017-06-2115-42/+41
| | | | llvm-svn: 305968
* Fix build.Rafael Espindola2017-06-211-1/+1
| | | | llvm-svn: 305967
* [codeview] respect signedness of APSInts when printing to YAMLBob Haarman2017-06-211-1/+1
| | | | | | | | | | | | | | | | | | Summary: This fixes a bug where we always treat APSInts in Codeview as signed when writing them to YAML. One symptom of this problem is that llvm-pdbdump raw would show Enumerator Values that differ between the original PDB and a PDB that has been round-tripped through YAML. Reviewers: zturner Reviewed By: zturner Subscribers: llvm-commits, fhahn Differential Revision: https://reviews.llvm.org/D34013 llvm-svn: 305965
* [AMDGPU] Combine add and adde, sub and subeStanislav Mekhanoshin2017-06-212-9/+81
| | | | | | | | | If one of the arguments of adde/sube is zero we can fold another add/sub into it. Differential Revision: https://reviews.llvm.org/D34374 llvm-svn: 305964
* Mark dump() methods as const. NFCSam Clegg2017-06-218-15/+15
| | | | | | | | | Add const qualifier to any dump() method where adding one was trivial. Differential Revision: https://reviews.llvm.org/D34481 llvm-svn: 305963
* [AMDGPU] simplify add x, *ext (setcc) => addc|subb x, 0, setccStanislav Mekhanoshin2017-06-214-0/+59
| | | | | | | | | This simplification allows to avoid generating v_cndmask_b32 to serialize condition code between compare and use. Differential Revision: https://reviews.llvm.org/D34300 llvm-svn: 305962
* Enable vectorizer-maximize-bandwidth by default.Dehao Chen2017-06-211-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: vectorizer-maximize-bandwidth is generally useful in terms of performance. I've tested the impact of changing this to default on speccpu benchmarks on sandybridge machines. The result shows non-negative impact: spec/2006/fp/C++/444.namd 26.84 -0.31% spec/2006/fp/C++/447.dealII 46.19 +0.89% spec/2006/fp/C++/450.soplex 42.92 -0.44% spec/2006/fp/C++/453.povray 38.57 -2.25% spec/2006/fp/C/433.milc 24.54 -0.76% spec/2006/fp/C/470.lbm 41.08 +0.26% spec/2006/fp/C/482.sphinx3 47.58 -0.99% spec/2006/int/C++/471.omnetpp 22.06 +1.87% spec/2006/int/C++/473.astar 22.65 -0.12% spec/2006/int/C++/483.xalancbmk 33.69 +4.97% spec/2006/int/C/400.perlbench 33.43 +1.70% spec/2006/int/C/401.bzip2 23.02 -0.19% spec/2006/int/C/403.gcc 32.57 -0.43% spec/2006/int/C/429.mcf 40.35 +0.27% spec/2006/int/C/445.gobmk 26.96 +0.06% spec/2006/int/C/456.hmmer 24.4 +0.19% spec/2006/int/C/458.sjeng 27.91 -0.08% spec/2006/int/C/462.libquantum 57.47 -0.20% spec/2006/int/C/464.h264ref 46.52 +1.35% geometric mean +0.29% The regression on 453.povray seems real, but is due to secondary effects as all hot functions are bit-identical with and without the flag. I started this patch to consult upstream opinions on this. It will be greatly appreciated if the community can help test the performance impact of this change on other architectures so that we can decided if this should be target-dependent. Reviewers: hfinkel, mkuper, davidxl, chandlerc Reviewed By: chandlerc Subscribers: rengolin, sanjoy, javed.absar, bjope, dorit, magabari, RKSimon, llvm-commits, mzolotukhin Differential Revision: https://reviews.llvm.org/D33341 llvm-svn: 305960
* [Hexagon] Use MachineInstrBuilder instead of changing instruction in placeKrzysztof Parzyszek2017-06-211-45/+9
| | | | llvm-svn: 305953
* Rename WinCOFFStreamer.cpp -> MCWinCOFFStreamer.cppSam Clegg2017-06-212-2/+2
| | | | | | | | | For consistency with other MC*Streamer.cpp files and the header file. Differential Revision: https://reviews.llvm.org/D34466 llvm-svn: 305952
* [Target] Implement the ".rdata" MIPS assembly directive.Davide Italiano2017-06-211-0/+22
| | | | | | | | Patch by John Baldwin < jhb at freebsd dot org >! Differential Revision: https://reviews.llvm.org/D34452 llvm-svn: 305949
* [Solaris] emit .init_array instead of .ctors on Solaris (Sparc/x86)Davide Italiano2017-06-215-0/+21
| | | | | | | | Patch by Fedor Sergeev. Differential Revision: https://reviews.llvm.org/D33868 llvm-svn: 305948
* [Reassociate] Use early returns in a couple places to reduce indentation and ↵Craig Topper2017-06-211-26/+26
| | | | | | improve readability. NFC llvm-svn: 305946
* [Reassociate] Const correct a helper function. NFCCraig Topper2017-06-211-2/+2
| | | | llvm-svn: 305945
* [DWARF] Support for DW_FORM_strx3 and complete support for DW_FORM_strx{1,2,4}Wolfgang Pieb2017-06-212-1/+24
| | | | | | | | | | (consumer). Reviewer: aprantl Differential Revision: https://reviews.llvm.org/D34418 llvm-svn: 305944
* [Hexagon] Handle more types of immediate operands in expand-condsetsKrzysztof Parzyszek2017-06-211-2/+13
| | | | llvm-svn: 305943
* [InstCombine] Cleanup using commutable matchers. Make a couple helper ↵Craig Topper2017-06-212-25/+19
| | | | | | methods standalone static functions. Put 'if' around variable declaration instead of after. NFC llvm-svn: 305941
* Add a "probe-stack" attributewhitequark2017-06-211-0/+7
| | | | | | | | | | | | | This attribute is used to ensure the guard page is triggered on stack overflow. Stack frames larger than the guard page size will generate a call to __probestack to touch each page so the guard page won't be skipped. Reviewed By: majnemer Differential Revision: https://reviews.llvm.org/D34386 llvm-svn: 305939
* [BasicAA] Use MayAlias instead of PartialAlias for fallback.Michael Kruse2017-06-211-5/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Using various methods, BasicAA tries to determine whether two GetElementPtr memory locations alias when its base pointers are known to be equal. When none of its heuristics are applicable, it falls back to PartialAlias to, according to a comment, protect TBAA making a wrong decision in case of unions and malloc. PartialAlias is not correct, because a PartialAlias result implies that some, but not all, bytes overlap which is not necessarily the case here. AAResults returns the first analysis result that is not MayAlias. BasicAA is always the first alias analysis. When it returns PartialAlias, no other analysis is queried to give a more exact result (which was the intention of returning PartialAlias instead of MayAlias). For instance, ScopedAA could return a more accurate result. The PartialAlias hack was introduced in r131781 (and re-applied in r132632 after some reverts) to fix llvm.org/PR9971 where TBAA returns a wrong NoAlias result due to a union. A test case for the malloc case mentioned in the comment was not provided and I don't think it is affected since it returns an omnipotent char anyway. Since r303851 (https://reviews.llvm.org/D33328) clang does emit specific TBAA for unions anymore (but "omnipotent char" instead). Hence, the PartialAlias workaround is not required anymore. This patch passes the test-suite and check-llvm/check-clang of a self-hoisted build on x64. Reviewed By: hfinkel Differential Revision: https://reviews.llvm.org/D34318 llvm-svn: 305938
* Object: Have the irsymtab builder take a string table builder. NFCI.Peter Collingbourne2017-06-211-17/+19
| | | | | | | | | This will be needed in order to share the irsymtab string table with the bitcode string table. Differential Revision: https://reviews.llvm.org/D33971 llvm-svn: 305937
* [CGP, memcmp] replace CreateZextOrTrunc with CreateZext because it can never ↵Sanjay Patel2017-06-211-5/+7
| | | | | | trunc llvm-svn: 305936
* [CGP] fix variables to be unsigned in memcmp expansionSanjay Patel2017-06-211-12/+14
| | | | llvm-svn: 305935
* Do not inline recursive direct calls in sample loader pass.Dehao Chen2017-06-211-0/+3
| | | | | | | | | | | | | | Summary: r305009 disables recursive inlining for indirect calls in sample loader pass. The same logic applies to direct recursive calls. Reviewers: iteratee, davidxl Reviewed By: iteratee Subscribers: sanjoy, llvm-commits, eraman Differential Revision: https://reviews.llvm.org/D34456 llvm-svn: 305934
* [PDB] Add symbols to the PDBReid Kleckner2017-06-211-0/+82
| | | | | | | | | | | | | | | | | | | Summary: The main complexity in adding symbol records is that we need to "relocate" all the type indices. Type indices do not have anything like relocations, an opaque data structure describing where to find existing type indices for fixups. The linker just has to "know" where the type references are in the symbol records. I added an overload of `discoverTypeIndices` that works on symbol records, and it seems to be able to link the standard library. Reviewers: zturner, ruiu Subscribers: llvm-commits, hiraditya Differential Revision: https://reviews.llvm.org/D34432 llvm-svn: 305933
* [PowerPC] define target hook isReallyTriviallyReMaterializable()Lei Huang2017-06-213-2/+29
| | | | | | | | | | | Define target hook isReallyTriviallyReMaterializable() to explicitly specify PowerPC instructions that are trivially rematerializable. This will allow the MachineLICM pass to accurately identify PPC instructions that should always be hoisted. Differential Revision: https://reviews.llvm.org/D34255 llvm-svn: 305932
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