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| author | Stanislav Mekhanoshin <Stanislav.Mekhanoshin@amd.com> | 2017-06-21 23:46:22 +0000 |
|---|---|---|
| committer | Stanislav Mekhanoshin <Stanislav.Mekhanoshin@amd.com> | 2017-06-21 23:46:22 +0000 |
| commit | 3ed38c601a7cfa7759766f321b8c03bc255a4fdd (patch) | |
| tree | aad2b000f5eb3e7518c6a863e3a52dca243c053f /llvm/lib | |
| parent | 72208a822615d458220858a6264a62e64635fcc9 (diff) | |
| download | bcm5719-llvm-3ed38c601a7cfa7759766f321b8c03bc255a4fdd.tar.gz bcm5719-llvm-3ed38c601a7cfa7759766f321b8c03bc255a4fdd.zip | |
[AMDGPU] Add FP_CLASS to the add/setcc combine
This is one of the nodes which also compile as v_cmp_*.
Differential Revision: https://reviews.llvm.org/D34485
llvm-svn: 305970
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/Target/AMDGPU/SIISelLowering.cpp | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp index ad9c5e49320..3563eb365b9 100644 --- a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp +++ b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp @@ -4872,7 +4872,9 @@ SDValue SITargetLowering::performAddCombine(SDNode *N, case ISD::SIGN_EXTEND: case ISD::ANY_EXTEND: { auto Cond = RHS.getOperand(0); - if (Cond.getOpcode() != ISD::SETCC) break; + if (Cond.getOpcode() != ISD::SETCC && + Cond.getOpcode() != AMDGPUISD::FP_CLASS) + break; SDVTList VTList = DAG.getVTList(MVT::i32, MVT::i1); SDValue Args[] = { LHS, DAG.getConstant(0, SL, MVT::i32), Cond }; Opc = (Opc == ISD::SIGN_EXTEND) ? ISD::SUBCARRY : ISD::ADDCARRY; |
