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* WebAssembly: more MCAsmInfo nits.JF Bastien2015-07-271-5/+1
| | | | | | | | | | Summary: As suggested by sunfish. Subscribers: jfb, llvm-commits, sunfish Differential Revision: http://reviews.llvm.org/D11544 llvm-svn: 243339
* [llvm-mc] Add --no-warn flag with -W alias to disable outputting warnings ↵Colin LeMahieu2015-07-272-1/+3
| | | | | | while assembling. llvm-svn: 243338
* IR: Expose the method 'getLocalSlot' in the module slot tracker.Alex Lorenz2015-07-271-0/+5
| | | | | | | | | | | This commit publicly exposes the method 'getLocalSlot' in the 'ModuleSlotTracker' class. This change is useful for MIR serialization, to serialize the unnamed basic block and unnamed alloca references. Reviewers: Duncan P. N. Exon Smith llvm-svn: 243336
* - Added support for parsing HWDiv features using Target Parser.Alexandros Lamprineas2015-07-273-21/+79
| | | | | | | - Architecture extensions are represented as a bitmap. Phabricator: http://reviews.llvm.org/D11457 llvm-svn: 243335
* [llvm-mc] Pushing plumbing through for --fatal-warnings flag.Colin LeMahieu2015-07-279-10/+10
| | | | llvm-svn: 243334
* [IndVars] Make loop varying predicates loop invariant.Sanjoy Das2015-07-272-5/+187
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: Was D9784: "Remove loop variant range check when induction variable is strictly increasing" This change re-implements D9784 with the two differences: 1. It does not use SCEVExpander and does not generate new instructions. Instead, it does a quick local search for existing `llvm::Value`s that it needs when modifying the `icmp` instruction. 2. It is more general -- it deals with both increasing and decreasing induction variables. I've added all of the tests included with D9784, and two more. As an example on what this change does (copied from D9784): Given C code: ``` for (int i = M; i < N; i++) // i is known not to overflow if (i < 0) break; a[i] = 0; } ``` This transformation produces: ``` for (int i = M; i < N; i++) if (M < 0) break; a[i] = 0; } ``` Which can be unswitched into: ``` if (!(M < 0)) for (int i = M; i < N; i++) a[i] = 0; } ``` I went back and forth on whether the top level logic should live in `SimplifyIndvar::eliminateIVComparison` or be put into its own routine. Right now I've put it under `eliminateIVComparison` because even though the `icmp` is not *eliminated*, it no longer is an IV comparison. I'm open to putting it in its own helper routine if you think that is better. Reviewers: reames, nicholas, atrick Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D11278 llvm-svn: 243331
* remove unnecessary forward declaration; NFCSanjay Patel2015-07-271-16/+12
| | | | llvm-svn: 243328
* don't repeat function names in comments; NFCSanjay Patel2015-07-271-61/+49
| | | | llvm-svn: 243327
* WebAssembly: minor MCAsmInfo fixesJF Bastien2015-07-271-1/+8
| | | | | | | | | | | | Summary: Fix pointer / callee-save stack sto size. Update comment character to be LISP-ish. Subscribers: llvm-commits, sunfish, jfb Differential Revision: http://reviews.llvm.org/D11537 llvm-svn: 243326
* MIR Serialization: Serialize the '.cfi_def_cfa_register' CFI instruction.Alex Lorenz2015-07-274-0/+15
| | | | llvm-svn: 243322
* MIR Parser: Rename the standalone parsing methods. NFC.Alex Lorenz2015-07-271-6/+7
| | | | | | | | This commit renames the methods 'parseMBB' and 'parseNamedRegister' to 'parseStandaloneMBB' and 'parseStandaloneNamedRegister' in order for their names to be consistent with the method 'parseStandaloneVirtualRegister'. llvm-svn: 243319
* Revert "[PeepholeOptimizer] Look through PHIs to find additional register ↵Bruno Cardoso Lopes2015-07-272-277/+83
| | | | | | | | sources" Still breaks some ARM buildbots. This reverts r243271. llvm-svn: 243318
* [LAA] Upper-case variable names, NFCAdam Nemet2015-07-271-4/+4
| | | | llvm-svn: 243313
* [LAA] Split out a helper from addRuntimeCheck to generate the check, NFCAdam Nemet2015-07-271-14/+18
| | | | llvm-svn: 243312
* [AArch64] Remove check for Darwin that was needed to decide if x18 shouldAkira Hatanaka2015-07-271-9/+7
| | | | | | | | | be reserved. The decision to reserve x18 is going to be made solely by the front-end, so it isn't necessary to check if the OS is Darwin in the backend. llvm-svn: 243308
* Fixed signed/unsigned comparison warning.Simon Pilgrim2015-07-271-1/+1
| | | | llvm-svn: 243306
* [InstCombine][X86][SSE] Replace sign/zero extension intrinsics with native IRSimon Pilgrim2015-07-271-14/+45
| | | | | | | | Now that we are generating sane codegen for vector sext/zext nodes on SSE targets, this patch uses instcombine to replace the SSE41/AVX2 pmovsx and pmovzx intrinsics with the equivalent native IR code. Differential Revision: http://reviews.llvm.org/D11503 llvm-svn: 243303
* Revert "Remove unnecessary null check. NFC."Pete Cooper2015-07-271-0/+3
| | | | | | | | | | | This reverts commit r243167. Duncan pointed out that dyn_cast can return null in these cases, so this was an unsafe commit to make. Sorry for the noise. Worryingly there were no tests which fail... llvm-svn: 243302
* Fix assert when inlining a constantexpr addrspacecastMatt Arsenault2015-07-271-2/+1
| | | | | | | | | | | | The pointer size of the addrspacecasted pointer might not have matched, so this would have hit an assert in accumulateConstantOffset. I think this was here to allow constant folding of a load of an addrspacecasted constant. Accumulating the offset through the addrspacecast doesn't make much sense, so something else is necessary to allow folding the load through this cast. llvm-svn: 243300
* Fix ODR violation. NFC.Diego Novillo2015-07-272-5/+5
| | | | | | | | There is an ODR conflict between lib/ExecutionEngine/ExecutionEngineBindings.cpp and lib/Target/TargetMachineC.cpp. The inline definitions should simply be marked static (thanks dblaikie for the hint). llvm-svn: 243298
* AMDGPU: don't match vgpr loads for constant loadsMarek Olsak2015-07-271-3/+0
| | | | | | | | | | | | Author: Dave Airlie <airlied@redhat.com> In order to implement indirect sampler loads, we don't want to match on a VGPR load but an SGPR one for constants, as we cannot feed VGPRs to the sampler only SGPRs. this should be applicable for llvm 3.7 as well. llvm-svn: 243294
* move combineRepeatedFPDivisors logic into a helper function; NFCISanjay Patel2015-07-271-42/+57
| | | | llvm-svn: 243293
* Reset the virtual registers in liveins when clearing the virtual registers.Alex Lorenz2015-07-271-0/+2
| | | | | | | | | This commit zeroes out the virtual register references in the machine function's liveins in the class 'MachineRegisterInfo' when the virtual register definitions are cleared. Reviewers: Matthias Braun llvm-svn: 243290
* MIR Serialization: Serialize the machine function's liveins.Alex Lorenz2015-07-274-0/+52
| | | | | Reviewers: Duncan P. N. Exon Smith llvm-svn: 243288
* fix typo and spacing; NFCSanjay Patel2015-07-271-2/+2
| | | | llvm-svn: 243287
* [TableGen] Emit the correct error message.Davide Italiano2015-07-271-1/+1
| | | | llvm-svn: 243284
* Revert "Add const to a bunch of Type* in DataLayout. NFC."Pete Cooper2015-07-271-13/+13
| | | | | | | | This reverts commit r243135. Feedback from Craig Topper and David Blaikie was that we don't put const on Type as it has no mutable state. llvm-svn: 243283
* Revert "Add const to some Type* parameters which didn't need to be mutable. ↵Pete Cooper2015-07-272-10/+10
| | | | | | | | | | NFC." This reverts commit r243146. Feedback from Craig Topper and David Blaikie was that we don't put const on Type as it has no mutable state. llvm-svn: 243282
* [PeepholeOptimizer] Look through PHIs to find additional register sourcesBruno Cardoso Lopes2015-07-272-83/+277
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Reapply r242295 with fixes in the implementation. - Teaches the ValueTracker in the PeepholeOptimizer to look through PHI instructions. - Add findNextSourceAndRewritePHI method to lookup into multiple sources returnted by the ValueTracker and rewrite PHIs with new sources. With these changes we can find more register sources and rewrite more copies to allow coaslescing of bitcast instructions. Hence, we eliminate unnecessary VR64 <-> GR64 copies in x86, but it could be extended to other archs by marking "isBitcast" on target specific instructions. The x86 example follows: A: psllq %mm1, %mm0 movd %mm0, %r9 jmp C B: por %mm1, %mm0 movd %mm0, %r9 jmp C C: movd %r9, %mm0 pshufw $238, %mm0, %mm0 Becomes: A: psllq %mm1, %mm0 jmp C B: por %mm1, %mm0 jmp C C: pshufw $238, %mm0, %mm0 Differential Revision: http://reviews.llvm.org/D11197 rdar://problem/20404526 llvm-svn: 243271
* [ARM/AArch64] Fix cost model for interleaved accessesSilviu Baranga2015-07-272-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | Summary: Fix the cost of interleaved accesses for ARM/AArch64. We were calling getTypeAllocSize and using it to check the number of bits, when we should have called getTypeAllocSizeInBits instead. This would pottentially cause the vectorizer to generate loads/stores and shuffles which cannot be matched with an interleaved access instruction. No performance changes are expected for now since matching/generating interleaved accesses is still disabled by default. Reviewers: rengolin Subscribers: aemerson, llvm-commits, rengolin Differential Revision: http://reviews.llvm.org/D11524 llvm-svn: 243270
* [X86] Reordered lowerVectorShuffleAsBitMask before ↵Simon Pilgrim2015-07-271-86/+86
| | | | | | | | lowerVectorShuffleAsBlend. NFCI. Allows us to show diffs for D11518 more clearly llvm-svn: 243264
* AMDGPU/SI: Fix the V_FRACT_F64 SI bug workaroundMarek Olsak2015-07-271-2/+2
| | | | | | This is a candidate for 3.7. llvm-svn: 243263
* LoopAccessAnalysis.cpp: Tweak r243239 to avoid side effects. It caused ↵NAKAMURA Takumi2015-07-271-3/+4
| | | | | | different emissions between gcc and clang. llvm-svn: 243258
* Avoid using uncommon acronym "MSROM".Sean Silva2015-07-271-2/+2
| | | | llvm-svn: 243256
* Roll forward r243250Jingyue Wu2015-07-262-4/+3
| | | | | | | | | r243250 appeared to break clang/test/Analysis/dead-store.c on one of the build slaves, but I couldn't reproduce this failure locally. Probably a false positive as I saw this test was broken by r243246 or r243247 too but passed later without people fixing anything. llvm-svn: 243253
* Revert r243250Jingyue Wu2015-07-262-3/+4
| | | | | | breaks tests llvm-svn: 243251
* [TTI/CostModel] improve TTI::getGEPCost and use it in ↵Jingyue Wu2015-07-262-4/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | CostModel::getInstructionCost Summary: This patch updates TargetTransformInfoImplCRTPBase::getGEPCost to consider addressing modes. It now returns TCC_Free when the GEP can be completely folded to an addresing mode. I started this patch as I refactored SLSR. Function isGEPFoldable looks common and is indeed used by some WIP of mine. So I extracted that logic to getGEPCost. Furthermore, I noticed getGEPCost wasn't directly tested anywhere. The best testing bed seems CostModel, but its getInstructionCost method invokes getAddressComputationCost for GEPs which provides very coarse estimation. So this patch also makes getInstructionCost call the updated getGEPCost for GEPs. This change inevitably breaks some tests because the cost model changes, but nothing looks seriously wrong -- if we believe the new cost model is the right way to go, these tests should be updated. This patch is not perfect yet -- the comments in some tests need to be updated. I want to know whether this is a right approach before fixing those details. Reviewers: chandlerc, hfinkel Subscribers: aschwaighofer, llvm-commits, aemerson Differential Revision: http://reviews.llvm.org/D9819 llvm-svn: 243250
* Implemented encoding and intrinsics of the following instructionsIgor Breger2015-07-263-96/+134
| | | | | | | | | | vunpckhps/pd, vunpcklps/pd, vpunpcklbw, vpunpckhbw, vpunpcklwd, vpunpckhwd, vpunpckldq, vpunpckhdq, vpunpcklqdq, vpunpckhqdq Added tests for intrinsics and encoding. Differential Revision: http://reviews.llvm.org/D11509 llvm-svn: 243246
* [LAA] Begin moving the logic of generating checks out of addRuntimeCheckAdam Nemet2015-07-261-69/+111
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: The goal is to start moving us closer to the model where RuntimePointerChecking will compute and store the checks. Then a client can filter the check according to its requirements and then use the filtered list of checks with addRuntimeCheck. Before the patch, this is all done in addRuntimeCheck. So the patch starts to split up addRuntimeCheck while providing the old API under what's more or less a wrapper now. The new underlying addRuntimeCheck takes a collection of checks now, expands the code for the bounds then generates the code for the checks. I am not completely happy with making expandBounds static because now it needs so many explicit arguments but I don't want to make the type PointerBounds part of LAI. This should get fixed when addRuntimeCheck is moved to LoopVersioning where it really belongs, IMO. Audited the assembly diff of the testsuite (including externals). There is a tiny bit of assembly churn that is due to the different order the code for the bounds is expanded now (MultiSource/Benchmarks/Prolangs-C/bison/conflicts.s and with LoopDist on 456.hmmer/fast_algorithms.s). Reviewers: hfinkel Subscribers: klimek, llvm-commits Differential Revision: http://reviews.llvm.org/D11205 llvm-svn: 243239
* [InstCombine][SSE4A] Standardized references to Length/Width and Index/Start ↵Simon Pilgrim2015-07-251-34/+31
| | | | | | to match AMD docs. NFCI. llvm-svn: 243226
* [LoopUnswitch] Improve loop unswitch pass to find trivial unswitch ↵Chen Li2015-07-251-20/+60
| | | | | | | | | | | | | | | | | conditions more effectively Summary: This patch improves trivial loop unswitch. The current trivial loop unswitch only checks if loop header's terminator contains a trivial unswitch condition. But if the loop header only has one reachable successor (due to intentionally or unintentionally missed code simplification), we should consider the successor as part of the loop header. Therefore, instead of stopping at loop header's terminator, we should keep traversing its successors within loop until reach a *real* conditional branch or switch (whose condition can not be constant folded). This change will enable a single -loop-unswitch pass to unswitch multiple trivial conditions (unswitch one trivial condition could open opportunity to unswitch another one in the same loop), while the old implementation can unswitch only one per pass. Reviewers: reames, broune Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D11481 llvm-svn: 243203
* [AArch64][FastISel] Always use an AND instruction when truncating to ↵Juergen Ributzka2015-07-251-31/+24
| | | | | | | | | | | | | | non-legal types. When truncating to non-legal types (such as i16, i8 and i1) always use an AND instruction to mask out the upper bits. This was only done when the source type was an i64, but not when the source type was an i32. This commit fixes this and adds the missing i32 truncate tests. This fixes rdar://problem/21990703. llvm-svn: 243198
* Fix PPCMaterializeInt to check the size of the integer based on theEric Christopher2015-07-251-9/+14
| | | | | | | | | | extension property we're requesting - zero or sign extended. This fixes cases where we want to return a zero extended 32-bit -1 and not be sign extended for the entire register. Also updated the already out of date comment with the current behavior. llvm-svn: 243192
* PPCMaterializeInt should only take a ConstantInt so represent this in the ↵Eric Christopher2015-07-251-12/+9
| | | | | | | | prototype and fix up all uses. llvm-svn: 243191
* [AArch64] Define subtarget feature "reserve-x18", which is used to decideAkira Hatanaka2015-07-254-10/+18
| | | | | | | | | | | | | | | | | whether register x18 should be reserved. This change is needed because we cannot use a backend option to set cl::opt "aarch64-reserve-x18" when doing LTO. Out-of-tree projects currently using cl::opt option "-aarch64-reserve-x18" to reserve x18 should make changes to add subtarget feature "reserve-x18" to the IR. rdar://problem/21529937 Differential Revision: http://reviews.llvm.org/D11463 llvm-svn: 243186
* DI/Verifier: Fix argument bitrot in DILocalVariableDuncan P. N. Exon Smith2015-07-241-0/+2
| | | | | | | | | | | | | | | | | | | | | | Add a verifier check that `DILocalVariable`s of tag `DW_TAG_arg_variable` always have a non-zero 'arg:' field, and those of tag `DW_TAG_auto_variable` always have a zero 'arg:' field. These are the only configurations that are properly understood by the backend. (Also, fix the bad examples in LangRef and test/Assembler, and fix the bug in Kaleidoscope Ch8.) A large number of testcases seem to have bitrotted their way forward from some ancient version of the debug info hierarchy that didn't have `arg:` parameters. If you have out-of-tree testcases that start failing in the verifier and you don't care enough to get the `arg:` right, you may have some luck just calling: sed -e 's/, arg: 0/, arg: 1/' or some such, but I hand-updated the ones in tree. llvm-svn: 243183
* MIR Serialization: Serialize MachineFrameInfo's callee saved information.Alex Lorenz2015-07-242-15/+60
| | | | | | | | | This commit serializes the callee saved information from the class 'MachineFrameInfo'. This commit extends the YAML mappings for the fixed and the ordinary stack objects and adds an optional 'callee-saved-register' attribute. This attribute is used to serialize the callee save information. llvm-svn: 243173
* Handle loop with negtive induction variable incrementLawrence Hu2015-07-241-37/+35
| | | | | | | | | | | | | This patch extend LoopReroll pass to hand the loops which is similar to the following: while (len > 1) { sum4 += buf[len]; sum4 += buf[len-1]; len -= 2; } llvm-svn: 243171
* Remove unnecessary null check. NFC.Pete Cooper2015-07-241-3/+0
| | | | | | | | Since both places which set this variable do so with dyn_cast, and not dyn_cast_or_null, its impossible to get a nullptr here, so we can remove the check. llvm-svn: 243167
* Use make_range(rbegin(), rend()) to allow foreach loops. NFC.Pete Cooper2015-07-2410-39/+26
| | | | | | | | | | | Instead of the pattern for (auto I = x.rbegin(), E = x.end(); I != E; ++I) we can use make_range to construct the reverse range and iterate using that instead. llvm-svn: 243163
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