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* [mips] Sink PredicateControl further down the class hierarchy.Simon Dardis2018-05-3011-68/+59
| | | | | | | | | | | | | | | | Previously PredicateControl in some cases was a member of <X>Inst classes for some X (DSP, EVA) or was in more irregular place in the hierarchry for any given instruction. This patch moves PredicateControl down to the root so that it is consistently available. Then correct the base class of microMIPS instructions as using EncodingPredicates instead of the general Predicates field of Instruction. Reviewers: smaksimovic, abeserminji, atanasyan Differential Revision: https://reviews.llvm.org/D47526 llvm-svn: 333536
* [mips] Correct the predicates of arithmetic and logic instructions.Simon Dardis2018-05-303-45/+79
| | | | | | | | | | | | As part of this effort, duplicate and correct the predicates of some aliases. Also disable code generation of some short form instructions for FastISel, as it would otherwise reject them. Reviewers: atanasyan, abeserminji, smaksimovic Differential Revision: https://reviews.llvm.org/D47075 llvm-svn: 333530
* AArch64: print correct annotation for ADRP addresses.Tim Northover2018-05-301-2/+2
| | | | | | | The immediate on an ADRP MCInst needs to be multiplied by 0x1000 to obtain the actual PC-offset that will be calculated. llvm-svn: 333525
* [AArch64][AsmParser] Fix segfault on illegal fpimm.Sander de Smalen2018-05-301-2/+2
| | | | | | | | | | | | | Floating point immediate combining a negative sign and a hexadecimal number, e.g. #-0x0 caused the compiler to crash. Reviewers: rengolin, fhahn, samparker, SjoerdMeijer, javed.absar Reviewed By: javed.absar Differential Revision: https://reviews.llvm.org/D47483 llvm-svn: 333524
* [Sparc] Treat %fxx registers with value type Other as single precisionDaniel Cederman2018-05-301-1/+1
| | | | | | | They get type Other when used in the clobber list in inline assembly. This fixes tests fp128.ll and float.ll that failed after r333512. llvm-svn: 333523
* Revert commit 333506Serge Pavlov2018-05-306-14/+40
| | | | | | | It looks like this commit is responsible for the fail: http://lab.llvm.org:8011/builders/sanitizer-x86_64-linux-autoconf/builds/24382. llvm-svn: 333518
* [Sparc] Select correct register class for FP register constraintsDaniel Cederman2018-05-301-0/+16
| | | | | | | | | | | | | | | | | Summary: The fX version of floating-point registers only supports single precision. We need to map the name to dX for doubles and qX for long doubles if we want getRegForInlineAsmConstraint() to be able to pick the correct register class. Reviewers: jyknight, venkatra Reviewed By: jyknight Subscribers: eraman, fedor.sergeev, jrtc27, llvm-commits Differential Revision: https://reviews.llvm.org/D47258 llvm-svn: 333512
* [X86] Add unmasked AVX512VNNI instrinsics. Use a select in IR instead.Craig Topper2018-05-301-0/+14
| | | | | | A future patch will remove the old masked intrinsics. llvm-svn: 333508
* Use uniform mechanism for OOM errors handlingSerge Pavlov2018-05-306-40/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is a recommit of r333390, which was reverted in r333395, because it caused cyclic dependency when building shared library `LLVMDemangle.so`. In this commit `ItaniumDemangler.cpp` was not changed. The original commit message is below. In r325551 many calls of malloc/calloc/realloc were replaces with calls of their safe counterparts defined in the namespace llvm. There functions generate crash if memory cannot be allocated, such behavior facilitates handling of out of memory errors on Windows. If the result of *alloc function were checked for success, the function was not replaced with the safe variant. In these cases the calling function made the error handling, like: T *NewElts = static_cast<T*>(malloc(NewCapacity*sizeof(T))); if (NewElts == nullptr) report_bad_alloc_error("Allocation of SmallVector element failed."); Actually knowledge about the function where OOM occurred is useless. Moreover having a single entry point for OOM handling is convenient for investigation of memory problems. This change removes custom OOM errors handling and replaces them with calls to functions `llvm::safe_*alloc`. Declarations of `safe_*alloc` are moved to a separate include file, to avoid cyclic dependency in SmallVector.h Differential Revision: https://reviews.llvm.org/D47440 llvm-svn: 333506
* [PowerPC] fix broken JIT-compiled code with tail call optimizationHiroshi Inoue2018-05-301-2/+3
| | | | | | | | | The relocation for branch instructions in the dynamic loader of ExecutionEngine assumes branch instructions with R_PPC64_REL24 relocation type are only bl. However, with the tail call optimization, b instructions can be also used to jump into another function. This patch makes the relocation to keep bits in the branch instruction other than the jump offset to avoid relocation rewrites a b instruction into bl. Differential Revision: https://reviews.llvm.org/D47456 llvm-svn: 333502
* MC: Remove redundant substr() callSam Clegg2018-05-302-2/+2
| | | | | | Differential Revision: https://reviews.llvm.org/D47047 llvm-svn: 333496
* [WebAssembly] MC: Add compile-twice test and fix corresponding bugSam Clegg2018-05-302-1/+2
| | | | | | Differential Revision: https://reviews.llvm.org/D47398 llvm-svn: 333494
* [PM/LoopUnswitch] When using the new SimpleLoopUnswitch pass, scheduleChandler Carruth2018-05-303-34/+61
| | | | | | | | | | | | | | | | | | | | | | loop-cleanup passes at the beginning of the loop pass pipeline, and re-enqueue loops after even trivial unswitching. This will allow us to much more consistently avoid simplifying code while doing trivial unswitching. I've also added a test case that specifically shows effective iteration using this technique. I've unconditionally updated the new PM as that is always using the SimpleLoopUnswitch pass, and I've made the pipeline changes for the old PM conditional on using this new unswitch pass. I added a bunch of comments to the loop pass pipeline in the old PM to make it more clear what is going on when reviewing. Hopefully this will unblock doing *partial* unswitching instead of just full unswitching. Differential Revision: https://reviews.llvm.org/D47408 llvm-svn: 333493
* [ORC] Fix an ambiguous make_unique call.Lang Hames2018-05-301-2/+2
| | | | llvm-svn: 333492
* [ORC] Update JITCompileCallbackManager to support multi-threaded code.Lang Hames2018-05-304-27/+110
| | | | | | | | | Previously JITCompileCallbackManager only supported single threaded code. This patch embeds a VSO (see include/llvm/ExecutionEngine/Orc/Core.h) in the callback manager. The VSO ensures that the compile callback is only executed once and that the resulting address cached for use by subsequent re-entries. llvm-svn: 333490
* [RISCV] Support resolving fixup_riscv_call and add to MCFixupKindInfo tableShiva Chen2018-05-301-1/+12
| | | | | | | | | | | | Resolving fixup_riscv_call by assembler when the linker relaxation diabled and the function and callsite within the same compile unit. And also adding static_assert after Infos array declaration to avoid missing any new fixup in MCFixupKindInfo in the future. Differential Revision: https://reviews.llvm.org/D47126 llvm-svn: 333487
* [VPlan] Replace LLVM_ATTRIBUTE_USED with ifndef NDEBUGDiego Caballero2018-05-291-2/+3
| | | | | | | | | | | | | Minor replacement. LLVM_ATTRIBUTE_USED was introduced to silence a warning but using #ifndef NDEBUG makes more sense in this case. Reviewers: dblaikie, fhahn, hsaito Reviewed By: dblaikie Differential Revision: https://reviews.llvm.org/D47498 llvm-svn: 333476
* [X86] Remove some of the extractelts from the new MOVSS+FMA patterns.Craig Topper2018-05-292-46/+55
| | | | | | | | We only need the extractelt that corresponds to the register we're trying to insert back into. We can't guarantee the others haven't been optimized out depending on how those operands were produced. So instead just look for an FR32/FR64 input and emit a COPY_TO_REGCLASS to VR128 in the output pattern. This matches what we do for ADD/SUB/MUL/DIV. llvm-svn: 333473
* [X86] Use VR128X instead of VR128 in EVEX instruction patterns.Craig Topper2018-05-291-23/+23
| | | | llvm-svn: 333464
* [X86] Rename the operands in the recently introduced MOVSS+FMA patterns so ↵Craig Topper2018-05-292-24/+24
| | | | | | | | that the operand names in the output pattern are always in 1, 2, 3 order since those are the operand names in the instruction. The order should be controlled in the input pattern. llvm-svn: 333463
* Fix build error introduced in rL333459Sam Clegg2018-05-291-2/+3
| | | | | | The DEBUG macro was renamed LLVM_DEBUG. llvm-svn: 333462
* [LoopInstSimplify] Re-implement the core logic of loop-instsimplify toChandler Carruth2018-05-292-115/+124
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | be both simpler and substantially more efficient. Rather than use a hand-rolled iteration technique that isn't quite the same as RPO, use the pre-built RPO loop body traversal utility. Once visiting the loop body in RPO, we can assert that we visit defs before uses reliably. When this is the case, the only need to iterate is when simplifying a def that is used by a PHI node along a back-edge. With this patch, the first pass over the loop body is just a complete simplification of every instruction across the loop body. When we encounter a use of a simplified instruction that stems from a PHI node in the loop body that has already been visited (due to some cyclic CFG, potentially the loop itself, or a nested loop, or unstructured control flow), we recall that specific PHI node for the second iteration. Nothing else needs to be preserved from iteration to iteration. On the second and later iterations, only instructions known to have simplified inputs are considered, each time starting from a set of PHIs that had simplified inputs along the backedges. Dead instructions are collected along the way, but deleted in a batch at the end of each iteration making the iterations themselves substantially simpler. This uses a new batch API for recursively deleting dead instructions. This alsa changes the routine to visit subloops. Because simplification is fundamentally transitive, we may need to visit the entire loop body, including subloops, to handle knock-on simplification. I've added a basic test file that helps demonstrate that all of these changes work. It includes both straight-forward loops with simplifications as well as interesting PHI-structures, CFG-structures, and a nested loop case. Differential Revision: https://reviews.llvm.org/D47407 llvm-svn: 333461
* [X86] Fix a potential crash that occur after r333419.Craig Topper2018-05-291-2/+1
| | | | | | The code could issue a truncate from a small type to larger type. We need to extend in that case instead. llvm-svn: 333460
* [WebAssembly] Add more error checking to object file parsingSam Clegg2018-05-291-224/+240
| | | | | | | | | | This should address some of the assert failures the fuzzer has been finding such as: https://bugs.chromium.org/p/oss-fuzz/issues/detail?id=6719 Differential Revision: https://reviews.llvm.org/D47086 llvm-svn: 333459
* AMDGPU: Fix typo in option descriptionMatt Arsenault2018-05-291-1/+1
| | | | llvm-svn: 333457
* AMDGPU: Round up kernel argument allocation sizeMatt Arsenault2018-05-293-5/+13
| | | | | | | | | | AFAIK the driver's allocation will actually have to round this up anyway. It is useful to track the rounded up size, so that the end of the kernel segment is known to be dereferencable so a wider s_load_dword can be used for a short argument at the end of the segment. llvm-svn: 333456
* [RISCV] Add peepholes for Global Address lowering patternsSameer AbuAsal2018-05-291-0/+208
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: Base and offset are always separated when a GlobalAddress node is lowered (rL332641) as an optimization to reduce instruction count. However, this optimization is not profitable if the Global Address ends up being used in only instruction. This patch adds peephole optimizations that merge an offset of an address calculation into the LUI %%hi and ADD %lo of the lowering sequence. The peephole handles three patterns: 1) ADDI (ADDI (LUI %hi(global)) %lo(global)), offset ---> ADDI (LUI %hi(global + offset)) %lo(global + offset). This generates: lui a0, hi (global + offset) add a0, a0, lo (global + offset) Instead of lui a0, hi (global) addi a0, hi (global) addi a0, offset This pattern is for cases when the offset is small enough to fit in the immediate filed of ADDI (less than 12 bits). 2) ADD ((ADDI (LUI %hi(global)) %lo(global)), (LUI hi_offset)) ---> offset = hi_offset << 12 ADDI (LUI %hi(global + offset)) %lo(global + offset) Which generates the ASM: lui a0, hi(global + offset) addi a0, lo(global + offset) Instead of: lui a0, hi(global) addi a0, lo(global) lui a1, (offset) add a0, a0, a1 This pattern is for cases when the offset doesn't fit in an immediate field of ADDI but the lower 12 bits are all zeros. 3) ADD ((ADDI (LUI %hi(global)) %lo(global)), (ADDI lo_offset, (LUI hi_offset))) ---> offset = global + offhi20<<12 + offlo12 ADDI (LUI %hi(global + offset)) %lo(global + offset) Which generates the ASM: lui a1, %hi(global + offset) addi a1, %lo(global + offset) Instead of: lui a0, hi(global) addi a0, lo(global) lui a1, (offhi20) addi a1, (offlo12) add a0, a0, a1 This pattern is for cases when the offset doesn't fit in an immediate field of ADDI and both the lower 1 bits and high 20 bits are non zero. Reviewers: asb Reviewed By: asb Subscribers: rbar, johnrusso, simoncook, jordy.potman.lists, apazos, niosHD, kito-cheng, shiva0217, zzheng, edward-jones, mgrang llvm-svn: 333455
* [BasicAA] Teach the analysis about atomic memcpyDaniel Neilson2018-05-291-1/+1
| | | | | | | | Summary: A simple change to derive mod/ref info from the atomic memcpy intrinsic in the same way as from the regular memcpy intrinsic. llvm-svn: 333454
* AMDGPU: Always set COMPUTE_PGM_RSRC2.ENABLE_TRAP_HANDLER to zero for AMDHSA asKonstantin Zhuravlyov2018-05-291-1/+2
| | | | | | | | it is set by CP Differential Revision: https://reviews.llvm.org/D47392 llvm-svn: 333451
* [ARM] Enable SETCCCARRY lowering for Thumb1.Eli Friedman2018-05-291-3/+1
| | | | | | | | | We've had Thumb1 support for ARMISD::SUBE for a while now, so this just works. Reduces codesize a bit for 64-bit integer comparisons. Differential Revision: https://reviews.llvm.org/D47387 llvm-svn: 333445
* IRBuilder: Add overload for intrinsics without argsMatt Arsenault2018-05-291-0/+8
| | | | llvm-svn: 333443
* AMDGPU: Pass function directly instead of MachineFunctionMatt Arsenault2018-05-298-36/+37
| | | | | | | These functions just query the underlying IR function, so pass it directly. llvm-svn: 333442
* AMDGPU: Add nuw to add off of kernarg ptrMatt Arsenault2018-05-291-2/+1
| | | | llvm-svn: 333441
* DAG: Remove redundant version of getRegisterTypeForCallingConvMatt Arsenault2018-05-295-22/+4
| | | | | | | | | | | There seems to be no real reason to have these separate copies. The existing implementations just copy each other for x86. For Mips there is a subtle difference, which is just a bug since it changes based on the context where which one was called. Dropping this version, all tests pass. If I try to merge them to match the removed version, a test fails. llvm-svn: 333440
* AMDGPU: Split R600 MCInst lowering into its own classTom Stellard2018-05-291-5/+29
| | | | | | | | | | Reviewers: arsenm, nhaehnle Subscribers: kzhuravl, wdng, yaxunl, dstuttard, tpr, llvm-commits, t-tye Differential Revision: https://reviews.llvm.org/D47307 llvm-svn: 333439
* TableGen: add some more helpful error messagesNicolai Haehnle2018-05-291-0/+13
| | | | | | | | | | | | | Summary: Change-Id: I6f3dacf675a4126134577616e259696bebdade3a Reviewers: tra, simon_tatham, craig.topper, MartinO, arsenm Subscribers: wdng, llvm-commits Differential Revision: https://reviews.llvm.org/D47429 Change-Id: I614de12a4c154c6d53c090f2f3e53ad2d09942c5 llvm-svn: 333436
* [StrictFP] Make getStrictFPOpcodeAction(...) more accessibleCameron McInally2018-05-291-32/+2
| | | | | | | | NFCI. This function will be reused in upcoming patches. Differential Revision: https://reviews.llvm.org/D47380 llvm-svn: 333433
* [AArch64] Fix PR32384: bump up the number of stores per memset and memcpyEvandro Menezes2018-05-292-5/+11
| | | | | | | | | | | | | As suggested in https://bugs.llvm.org/show_bug.cgi?id=32384#c1, this change makes the inlining of `memset()` and `memcpy()` more aggressive when compiling for speed. The tuning remains the same when optimizing for size. Patch by: Sebastian Pop <s.pop@samsung.com> Evandro Menezes <e.menezes@samsung.com> Differential revision: https://reviews.llvm.org/D45098 llvm-svn: 333429
* [mips] Process numeric register name in the .set assignment directiveSimon Atanasyan2018-05-291-8/+44
| | | | | | | | | | | | | | | | | | | | | | | | Now LLVM assembler cannot process the following code and generates an error. GNU tools support .set assignment directive with numeric register name. ``` .set r4, 4 test.s:1:11: error: invalid token in expression .set r4, $4 ^ ``` This patch teach assembler to handle such directives correctly. Unfortunately a numeric register name cannot be represented as an expression. That's why we have to maintain a separate `StringMap` in the `MipsAsmParser` to keep mapping between aliases names and register numbers. Differential revision: https://reviews.llvm.org/D47464 llvm-svn: 333428
* Revert "[AArch64] added FP16 vcvth intrinsic support"Amara Emerson2018-05-292-36/+5
| | | | | | This reverts commit r333410 due to bot failures. llvm-svn: 333427
* [AArch64][SVE] Asm: Support for predicated LSL/LSR (vectors)Sander de Smalen2018-05-292-0/+35
| | | | | | | | | | Reviewers: rengolin, huntergr, fhahn, samparker, SjoerdMeijer, javed.absar Reviewed By: SjoerdMeijer Differential Revision: https://reviews.llvm.org/D47365 llvm-svn: 333422
* [CodeView] Add prefix to CodeView registers.Jonas Devlieghere2018-05-292-116/+116
| | | | | | | | | | | | | Adds CVReg to CodeView register names to prevent a duplicate symbol with CR3 defined in termios.h, as suggested by Zachary on the mailing list. http://lists.llvm.org/pipermail/llvm-dev/2018-May/123372.html Differential revision: https://reviews.llvm.org/D47478 rdar://39863705 llvm-svn: 333421
* [X86] Scalar mask and scalar move optimizationsAlexander Ivchenko2018-05-294-135/+256
| | | | | | | | | | | | | | 1. Introduction of mask scalar TableGen patterns. 2. Introduction of new scalar move TableGen patterns and refactoring of existing ones. 3. Folding of pattern created by introducing scalar masking in Clang header files. Patch by tkrupa Differential Revision: https://reviews.llvm.org/D47012 llvm-svn: 333419
* StackColoring: better handling of statically unreachable codeThan McIntosh2018-05-291-2/+5
| | | | | | | | | | | | | | | | Summary: Avoid assert/crash during liveness calculation in situations where the incoming machine function has statically unreachable BBs. Second attempt at submitting; this version of the change includes a revised testcase. Fixes PR37130. Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D47372 llvm-svn: 333416
* [PowerPC] Fix the incorrect iterator inside peepholeLei Huang2018-05-291-6/+3
| | | | | | | | | | | | Instruction selection can insert nodes into the underlying list after the root node so iterating will thereby miss it. We should NOT assume that, the root node is the last element in the DAG nodelist. Patch by: steven.zhang (Qing Shan Zhang) Differential Revision: https://reviews.llvm.org/D47437 llvm-svn: 333415
* [AArch64][SVE] Asm: Support for AND, ORR, EOR and BIC instructions.Sander de Smalen2018-05-292-1/+47
| | | | | | | | | | | | | | | | | | | | | This patch addresses the following variants: - bitmask immediate, e.g. 'and z0.d, z0.d, #0x6'. - unpredicated data vectors, e.g. 'and z0.d, z1.d, z2.d'. - predicated data vectors, e.g. 'and z0.d, p0/m, z0.d, z1.d'. And also several aliases, such as: - ORN, alias of ORR. - EON, alias of EOR. - BIC, alias of AND (immediate variant) - MOV, alias of ORR (if unpredicated and source register operands are the same) Reviewers: rengolin, huntergr, fhahn, samparker, SjoerdMeijer, javed.absar Reviewed By: fhahn Differential Revision: https://reviews.llvm.org/D47363 llvm-svn: 333414
* [AArch64] added FP16 vcvth intrinsic supportLuke Geeson2018-05-292-5/+36
| | | | | | | | | | | | | | Summary: Change-Id: I0df845749c7689dfc99150ba7c19c7d0dadbd705 Reviewers: javed.absar, SjoerdMeijer Reviewed By: SjoerdMeijer Subscribers: llvm-commits, SjoerdMeijer Differential Revision: https://reviews.llvm.org/D46311 llvm-svn: 333410
* [mips] Emit R_MICROMIPS_GPREL16/R_MICROMIPS_SUB/R_MICROMIPS_LO16 / HI16 ↵Simon Atanasyan2018-05-294-12/+36
| | | | | | | | | | | | | relocations Emit R_MICROMIPS_GPREL16/R_MICROMIPS_SUB/R_MICROMIPS_LO16 and R_MICROMIPS_GPREL16/R_MICROMIPS_SUB/R_MICROMIPS_HI16 chains of relocations for %lo(%neg(%gp_rel())) and %hi(%neg(%gp_rel())) expressions in case of microMIPS. Differential Revision: http://reviews.llvm.org/D47220 llvm-svn: 333409
* [AArch64][SVE] Asm: Support for ADD (immediate) instructions.Sander de Smalen2018-05-294-15/+90
| | | | | | | | | | | | | | | | | | | This patch adds addsub_imm8_opt_lsl_(i8|i16|i32|i64) operands that are unsigned values in the range 0 to 255. For element widths of 16 bits or higher it may also be a signed multiple of 256 in the range 0 to 65280. Note: This also does some refactoring to reuse convenience function getShiftedVal<shift>(), and now allows AArch64 scalar 'ADD #-4096' to be accepted to be mapped to SUB #4096. Reviewers: rengolin, fhahn, samparker, SjoerdMeijer, javed.absar Reviewed By: fhahn Differential Revision: https://reviews.llvm.org/D47310 llvm-svn: 333408
* [mips] Emit R_MICROMIPS_HIGHER / R_MICROMIPS_HIGHEST relocationsSimon Atanasyan2018-05-294-4/+18
| | | | | | | | | | | Emit R_MICROMIPS_HIGHER / R_MICROMIPS_HIGHEST relocations for %higher() and %highest() expressions in case of microMIPS. These relocations do exactly the same things as R_MIPS_HIGHER / R_MIPS_HIGHEST, but for consistency it's better to write microMIPS variants. Differential Revision: http://reviews.llvm.org/D47219 llvm-svn: 333407
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