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* [GlobalISel] Introduce an instruction selector.Ahmed Bougacha2016-07-2714-2/+425
| | | | | | | | And implement it for AArch64, supporting x/w ADD/OR. Differential Revision: https://reviews.llvm.org/D22373 llvm-svn: 276875
* [AArch64] Mark various *Info classes as 'final'. NFC.Ahmed Bougacha2016-07-275-5/+5
| | | | llvm-svn: 276874
* [AArch64] Define AArch64RegisterInfo as a class, not a struct. NFC.Ahmed Bougacha2016-07-271-2/+1
| | | | llvm-svn: 276873
* [mips][ias] Check '$rs = $rd' constraints when both registers are in AsmText.Daniel Sanders2016-07-272-38/+86
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: This is one possible solution to the problem of ignoring constraints that Simon raised in D21473 but it's a bit of a hack. The integrated assembler currently ignores violations of the tied register constraints when the operands involved in a tie are both present in the AsmText. For example, 'dati $rs, $rt, $imm' with the '$rs = $rt' will silently replace $rt with $rs. So 'dati $2, $3, 1' is processed as if the user provided 'dati $2, $2, 1' without any diagnostic being emitted. This is difficult to solve properly because there are multiple parts of the matcher that are silently forcing these constraints to be met. Tied operands are rendered to instructions by cloning previously rendered operands but this is unnecessary because the matcher was already instructed to render the operand it would have cloned. This is also unnecessary because earlier code has already replaced the MCParsedOperand with the one it was tied to (so the parsed input is matched as if it were 'dati <RegIdx 2>, <RegIdx 2>, <Imm 1>'). As a result, it looks like fixing this properly amounts to a rewrite of the tied operand handling which affects all targets. This patch however, merely inserts a checking hook just before the substitution of MCParsedOperands and the Mips target overrides it. It's not possible to accurately check the registers are the same this early (because numeric registers haven't been bound to a register class yet) so it cheats a bit and checks that the tokens that produced the operand are lexically identical. This works because tied registers need to have the same register class but it does have a flaw. It will reject 'dati $4, $a0, 1' for violating the constraint even though $a0 ends up as the same register as $4. Reviewers: sdardis Subscribers: dsanders, llvm-commits, sdardis Differential Revision: https://reviews.llvm.org/D21994 llvm-svn: 276867
* [PowerPC] Fix typo in PPCHazardRecognizers.cppNemanja Ivanovic2016-07-271-1/+1
| | | | | | Fixes PR28731. llvm-svn: 276865
* PowerPC: Avoid implicit iterator conversions, NFCDuncan P. N. Exon Smith2016-07-277-174/+170
| | | | | | | | | | | | | | | | | Avoid implicit conversions from MachineInstrBundleIterator to MachineInstr* in the PowerPC backend, mainly by preferring MachineInstr& over MachineInstr* when a pointer isn't nullable and using range-based for loops. There was one piece of questionable code in PPCInstrInfo::AnalyzeBranch, where a condition checked a pointer converted from an iterator for nullptr. Since this case is impossible (moreover, the code above guarantees that the iterator is valid), I removed the check when I changed the pointer to a reference. Despite that case, there should be no functionality change here. llvm-svn: 276864
* [ARM] Set a non-conflicting comment character for assembly in MSVC modeRenato Golin2016-07-271-0/+1
| | | | | | | | | | | | | | | | | | | | | | | Currently, for ARMCOFFMCAsmInfoMicrosoft, no comment character is set, thus the idefault, '#', is used. The hash character doesn't work as comment character in ARM assembly, since '#' is used for immediate values. The comment character is set to ';', which is the comment character used by MS armasm.exe. (The microsoft armasm.exe uses a different directive syntax than what LLVM currently supports though, similar to ARM's armasm.) This allows inline assembly with immediate constants to be built (and brings the assembly output from clang -S closer to being possible to assemble). A test is added that verifies that ';' is correctly interpreted as comments in this mode, and verifies that assembling code that includes literal constants with a '#' works. Patch by Martin Storsjö. llvm-svn: 276859
* Revert r276856 "Adjust Registry interface to not require plugins to export a ↵John Brawn2016-07-272-4/+0
| | | | | | | | registry" This is causing a huge pile of buildbot failures. llvm-svn: 276857
* Adjust Registry interface to not require plugins to export a registryJohn Brawn2016-07-272-0/+4
| | | | | | | | | | | | | | | | | | | | Currently the Registry class contains the vestiges of a previous attempt to allow plugins to be used on Windows without using BUILD_SHARED_LIBS, where a plugin would have its own copy of a registry and export it to be imported by the tool that's loading the plugin. This only works if the plugin is entirely self-contained with the only interface between the plugin and tool being the registry, and in particular this conflicts with how IR pass plugins work. This patch changes things so that instead the add_node function of the registry is exported by the tool and then imported by the plugin, which solves this problem and also means that instead of every plugin having to export every registry they use instead LLVM only has to export the add_node functions. This allows plugins that use a registry to work on Windows if LLVM_EXPORT_SYMBOLS_FOR_PLUGINS is used. Differential Revision: http://reviews.llvm.org/D21385 llvm-svn: 276856
* [DAGCombiner] Use APInt directly to detect out of range shift constantsSimon Pilgrim2016-07-271-3/+3
| | | | | | | | Using getZExtValue() will assert if the value doesn't fit into uint64_t - SHL was already doing this, I've just updated ASHR/LSHR to match As mentioned on D22726 llvm-svn: 276855
* [MBP] Added some more debug messages and some clean ups /NFCSjoerd Meijer2016-07-271-11/+31
| | | | | | Differential Revision: https://reviews.llvm.org/D22669 llvm-svn: 276849
* Refactor - CodeExtractor : Move check for valid block to static utilitySean Silva2016-07-271-2/+2
| | | | | | | | | | | This lets you actually check to see if a block is valid before trying to extract. Patch by River Riddle! Differential Revision: https://reviews.llvm.org/D22699 llvm-svn: 276846
* [GVNHoist] Fix typo in assert.George Burgess IV2016-07-271-1/+1
| | | | | | This fixes PR28730. llvm-svn: 276844
* [MC] Add command-line option to choose the max nest level in asm macros.Davide Italiano2016-07-271-4/+17
| | | | | | | Submitted by: t83wCSLq Differential Revision: https://reviews.llvm.org/D22313 llvm-svn: 276842
* GVN-hoist: improve code generation for recursive GEPsSebastian Pop2016-07-271-42/+82
| | | | | | | | | | | | | | | | | | | When loading or storing in a field of a struct like "a.b.c", GVN is able to detect the equivalent expressions, and GVN-hoist would fail in the code generation. This is because the GEPs are not hoisted as scalar operations to avoid moving the GEPs too far from their ld/st instruction when the ld/st is not movable. So we end up having to generate code for the GEP of a ld/st when we move the ld/st. In the case of a GEP referring to another GEP as in "a.b.c" we need to code generate all the GEPs necessary to make all the operands available at the new location for the ld/st. With this patch we recursively walk through the GEP operands checking whether all operands are available, and in the case of a GEP operand, it recursively makes all its operands available. Code generation happens from the inner GEPs out until reaching the GEP that appears as an operand of the ld/st. Differential Revision: https://reviews.llvm.org/D22599 llvm-svn: 276841
* GVN-hoist: use DFS numbers instead of walking the instruction streamSebastian Pop2016-07-271-10/+3
| | | | | | | | | The patch replaces a function that walks the IR with a call to firstInBB() that uses the DFS numbering. NFC. Differential Revision: https://reviews.llvm.org/D22809 llvm-svn: 276840
* add a verbose mode to Loop->print() to print all the basic blocks of a loopSebastian Pop2016-07-271-0/+4
| | | | | | Differential Revision: https://reviews.llvm.org/D22817 llvm-svn: 276838
* [ConstantFolding] Correctly handle failures in ↵David Majnemer2016-07-271-4/+13
| | | | | | | | | | | ConstantFoldConstantExpressionImpl Failures in ConstantFoldConstantExpressionImpl were ignored causing crashes down the line. This fixes PR28725. llvm-svn: 276827
* Reverting r276771 due to MSan failures.Andrew Kaylor2016-07-274-50/+0
| | | | llvm-svn: 276824
* AMDGPU: Use rcp for fdiv 1, x with fpmath metadataMatt Arsenault2016-07-261-1/+1
| | | | | | | Using rcp should be OK for safe math usually, so this should not be replacing the original fdiv. llvm-svn: 276823
* Revert r276136 "Use ValueOffsetPair to enhance value reuse during SCEV ↵Hans Wennborg2016-07-262-80/+33
| | | | | | | | | | expansion." It causes Clang tests to fail after Windows self-host (PR28705). (Also reverts follow-up r276139.) llvm-svn: 276822
* AMDGPU: Use implicit_def for selecting anyextMatt Arsenault2016-07-261-4/+7
| | | | llvm-svn: 276819
* MIRParser: Use dot instead of colon to mark subregistersMatthias Braun2016-07-264-6/+14
| | | | | | | | | | | | | | | | | Change the syntax to use `%0.sub8` to denote a subregister. This seems like a more natural fit to denote subregisters; I also plan to introduce a new ":classname" syntax in upcoming patches to denote the register class of a vreg. Note that this commit disallows plain identifiers to start with a '.' character. This shouldn't affect anything as external names/IR references are all prefixed with '$'/'%', plain identifiers are only used for instruction names, register mask names and subreg indexes. Differential Revision: https://reviews.llvm.org/D22390 llvm-svn: 276815
* AMDGPU/R600: Remove dead custom insertersMatt Arsenault2016-07-261-209/+1
| | | | | | The intrinsics for these were removed, so this is dead. llvm-svn: 276805
* AMDGPU: Minor AsmPrinter cleanupsMatt Arsenault2016-07-261-79/+84
| | | | llvm-svn: 276804
* [Hexagon] Post-increment loads/stores enhancementsKrzysztof Parzyszek2016-07-265-112/+99
| | | | | | | - Generate vector post-increment stores more aggressively. - Predicate post-increment and vector stores in early if-conversion. llvm-svn: 276800
* GlobalISel: add generic load and store instructions.Tim Northover2016-07-262-0/+71
| | | | | | | Pretty straightforward, the only oddity is the MachineMemOperand (which it's surprisingly difficult to share code for). llvm-svn: 276799
* [X86] Split out absdiff detection from SAD combine. NFC.Michael Kuperstein2016-07-261-59/+64
| | | | | | Preparation for supporting PSADBW emission for straight-line code. llvm-svn: 276798
* [Hexagon] Gracefully handle reg class mismatch in HexagonLoopRescheduleKrzysztof Parzyszek2016-07-261-13/+19
| | | | llvm-svn: 276793
* [Hexagon] Rerun bit tracker on new instructions in RIEKrzysztof Parzyszek2016-07-263-5/+17
| | | | | | | | | | | | | | | | | | | Consider this case: vreg1 = A2_zxth vreg0 (1) ... vreg2 = A2_zxth vreg1 (2) Redundant instruction elimination could delete the instruction (1) because the user (2) only cares about the low 16 bits. Then it could delete (2) because the input is already zero-extended. The problem is that the properties allowing each individual instruction to be deleted depend on the existence of the other instruction, so either one can be deleted, but not both. The existing check for this situation in RIE was insufficient. The fix is to update all dependent cells when an instruction is removed (replaced via COPY) in RIE. llvm-svn: 276792
* [Hexagon] Bitwise operations for insert/extract word not simplifiedKrzysztof Parzyszek2016-07-262-25/+85
| | | | | | | Change the bit simplifier to generate REG_SEQUENCE instructions in addition to COPY, which will handle cases of word insert/extract. llvm-svn: 276787
* MIRParser: Use shorter cfi identifiersMatthias Braun2016-07-262-10/+10
| | | | | | | | | | | | | | | | In an instruction like: CFI_INSTRUCTION .cfi_def_cfa ... we can drop the '.cfi_' prefix since that should be obvious by the context: CFI_INSTRUCTION def_cfa ... While being a terser and cleaner syntax this also prepares to dropping support for identifiers starting with a dot character so we can use it for expressions. Differential Revision: http://reviews.llvm.org/D22388 llvm-svn: 276785
* [MC] Don't crash when trying to emit a relocation against .bss.Davide Italiano2016-07-261-2/+2
| | | | | | Turn that into an error instead. llvm-svn: 276783
* [InstSimplify] Cast folding can be made more genericDavid Majnemer2016-07-261-46/+43
| | | | | | Use isEliminableCastPair to determine if a pair of casts are foldable. llvm-svn: 276777
* [LoopUtils] Sort headersAdam Nemet2016-07-261-3/+4
| | | | llvm-svn: 276776
* GlobalISel: add correct operand type to G_FRAME_INDEX instrs.Tim Northover2016-07-261-1/+1
| | | | | | Frame indices should use "addFrameIndex", not "addImm". llvm-svn: 276775
* [Hexagon] Add support for proper handling of H and L constraintsKrzysztof Parzyszek2016-07-261-8/+16
| | | | | | | | | H -> High part of reg pair. L -> Low part of reg pair. Patch by Sundeep Kushwaha. llvm-svn: 276773
* GlobalISel: omit braces on MachineInstr types when there's only one.Tim Northover2016-07-262-8/+15
| | | | | | Tidies up the representation a bit in the common case. llvm-svn: 276772
* Re-committing r275284: add support to inline __builtin_mempcpyAndrew Kaylor2016-07-264-0/+50
| | | | | | | | Patch by Sunita Marathe Differential Revision: http://reviews.llvm.org/D21920 llvm-svn: 276771
* AMDGPU: Make AMDGPUMachineFunction fields privateMatt Arsenault2016-07-2610-56/+80
| | | | | | | | | ABIArgOffset is a problem because properly fsetting the KernArgSize requires that the reserved area before the real kernel arguments be correctly aligned, which requires fixing clover. llvm-svn: 276766
* AMDGPU: Add fp legacy instruction intrinsicsMatt Arsenault2016-07-265-2/+21
| | | | | | | This could use some additional optimization work to use mad/mac legacy. llvm-svn: 276764
* GlobalISel: add specialized buildCopy function to MachineInstrBuilder.Tim Northover2016-07-263-3/+7
| | | | | | NFC. llvm-svn: 276763
* GlobalISel: give MachineInstrBuilder a uniform interface. NFC.Tim Northover2016-07-262-50/+12
| | | | | | | | | | | Instead of an ad-hoc collection of "buildInstr" functions with varying numbers of registers, this uses variadic templates to provide for as many regs as needed! Also make IRtranslator use new "buildBr" function instead of some weird generic one that no-one else would really use. llvm-svn: 276762
* [mips] Fix typos in spelling of lowerRETURNADDR.Daniel Sanders2016-07-263-3/+3
| | | | | | The first letter was mistakenly capitalized. llvm-svn: 276753
* [Hexagon] Update store offset when not packetizing it with allocframeKrzysztof Parzyszek2016-07-262-15/+51
| | | | | | | | | | When the packetizer wants to put a store to a stack slot in the same packet with an allocframe, it updates the store offset to reflect the value of SP before it is updated by allocframe. If the store cannot be packetized with the allocframe after all, the offset needs to be updated back to the previous value. llvm-svn: 276749
* [ARM] Improve error messages for .arch_extension directiveOliver Stannard2016-07-261-4/+8
| | | | | | | | | | | | - More informative message when extension name is not an identifier token. - Stop parsing directive if extension is unknown (avoid duplicate error messages). - Report unsupported extensions with a source location, rather than report_fatal_error. Differential Revision: https://reviews.llvm.org/D22806 llvm-svn: 276748
* [ARM] Implement -mimplicit-it assembler optionOliver Stannard2016-07-263-38/+334
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This option, compatible with gas's -mimplicit-it, controls the generation/checking of implicit IT blocks in ARM/Thumb assembly. This option allows two behaviours that were not possible before: - When in ARM mode, emit a warning when assembling a conditional instruction that is not in an IT block. This is enabled with -mimplicit-it=never and -mimplicit-it=thumb. - When in Thumb mode, automatically generate IT instructions when an instruction with a condition code appears outside of an IT block. This is enabled with -mimplicit-it=thumb and -mimplicit-it=always. The default option is -mimplicit-it=arm, which matches the existing behaviour (allow conditional ARM instructions outside IT blocks without warning, and error if a conditional Thumb instruction is outside an IT block). The general strategy for generating IT blocks in Thumb mode is to keep a small list of instructions which should be in the IT block, and only emit them when we encounter something in the input which means we cannot continue the block. This could be caused by: - A non-predicable instruction - An instruction with a condition not compatible with the IT block - The IT block already contains 4 instructions - A branch-like instruction (including ALU instructions with the PC as the destination), which cannot appear in the middle of an IT block - A label (branching into an IT block is not legal) - A change of section, architecture, ISA, etc - The end of the assembly file. Some of these, such as change of section and end of file, are parsed outside of the ARM asm parser, so I've added a new virtual function to AsmParser to ensure any previously-parsed instructions have been emitted. The ARM implementation of this flushes the currently pending IT block. We now have to try instruction matching up to 3 times, because we cannot know if the current IT block is valid before matching, and instruction matching changes depending on the IT block state (due to the 16-bit ALU instructions, which set the flags iff not in an IT block). In the common case of not having an open implicit IT block and the instruction being matched not needing one, we still only have to run the matcher once. I've removed the ITState.FirstCond variable, because it does not store any information that isn't already represented by CurPosition. I've also updated the comment on CurPosition to accurately describe it's meaning (which this patch doesn't change). Differential Revision: https://reviews.llvm.org/D22760 llvm-svn: 276747
* [X86][SSE] Fixed issue with memory folding of (v)cvtsd2ss intrinsicsSimon Pilgrim2016-07-261-2/+2
| | | | | | | | Fixed typo in the intrinsic definitions of (v)cvtsd2ss with memory folding. This was only unearthed when rL276102 started using the intrinsic again..... llvm-svn: 276740
* [mips] MIPS64R6 compact branch supportSimon Dardis2016-07-265-11/+98
| | | | | | | | | | | | | MIPS64R6 compact branch support. As the MIPS LLVM backend uses distinct MachineInstrs for certain 32 and 64 bit instructions (e.g. BEQ & BEQ64) that map to the same instruction, extend compact branch support for the corresponding 64bit branches. Reviewers: dsanders Differential Revision: https://reviews.llvm.org/D20164 llvm-svn: 276739
* Fixed spelling in commentSimon Pilgrim2016-07-261-1/+1
| | | | llvm-svn: 276738
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