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* New bitcode linker flags:Artem Belevich2015-09-011-13/+33
| | | | | | | | | -only-needed -- link in only symbols needed by destination module -internalize -- internalize linked symbols Differential Revision: http://reviews.llvm.org/D12459 llvm-svn: 246561
* [AArch64] Lower READCYCLECOUNTER using MRS PMCCTNR_EL0.Ahmed Bougacha2015-09-015-6/+25
| | | | | | | | | | This matches the ARM behavior. In both cases, the register is part of the optional Performance Monitors extension, so, add the feature, and enable it for the A-class processors we support. Differential Revision: http://reviews.llvm.org/D12425 llvm-svn: 246555
* [MC] Allow MCObjectWriter's output stream to be swapped outDavid Majnemer2015-09-013-79/+58
| | | | | | | | | | | | | | | | | | There are occasions where it is useful to consider the entirety of the contents of a section. For example, compressed debug info needs the entire section available before it can compress it and write it out. The compressed debug info scenario was previously implemented by mirroring the implementation of writeSectionData in the ELFObjectWriter. Instead, allow the output stream to be swapped on demand. This lets callers redirect the output stream to a more convenient location before it hits the object file. No functionality change is intended. Differential Revision: http://reviews.llvm.org/D12509 llvm-svn: 246554
* AVX512: Implemented intrinsics for valign.Igor Breger2015-09-011-0/+8
| | | | | | Differential Revision: http://reviews.llvm.org/D12526 llvm-svn: 246551
* [AArch64] Turn on by default interleaved access vectorizationSilviu Baranga2015-09-011-0/+2
| | | | | | | | | | | | | | | | | Summary: This change turns on by default interleaved access vectorization for AArch64. We also clean up some tests which were spedifically enabling this behaviour. Reviewers: rengolin Subscribers: aemerson, llvm-commits, rengolin Differential Revision: http://reviews.llvm.org/D12149 llvm-svn: 246542
* [ARM] Turn on by default interleaved access vectorizationSilviu Baranga2015-09-011-0/+2
| | | | | | | | | | | | | | Summary: This change turns on by default interleaved access vectorization on ARM, as it has shown to be beneficial on ARM. Reviewers: rengolin Subscribers: aemerson, llvm-commits, rengolin Differential Revision: http://reviews.llvm.org/D12146 llvm-svn: 246541
* [ARM][AArch64] Turn on by default interleaved access loweringSilviu Baranga2015-09-011-1/+1
| | | | | | | | | | | | | | | | | Summary: Interleaved access lowering removes a memory operation and a sequence of vector shuffles and replaces it with a series of memory operations. This should be always beneficial. This pass in only enabled on ARM/AArch64. Reviewers: rengolin Subscribers: aemerson, llvm-commits, rengolin Differential Revision: http://reviews.llvm.org/D12145 llvm-svn: 246540
* Fix typo.Yaron Keren2015-09-011-1/+1
| | | | llvm-svn: 246538
* AMDGPU: Fix adding redundant implicit operandsMatt Arsenault2015-09-011-11/+7
| | | | | | | These are already added during the MachineInstr construction, so this was adding the implicit registers twice. llvm-svn: 246525
* Distribute the weight on the edge from switch to default statement to edges ↵Cong Hou2015-09-013-21/+43
| | | | | | | | | | | | | | | | | | | generated in lowering switch. Currently, when edge weights are assigned to edges that are created when lowering switch statement, the weight on the edge to default statement (let's call it "default weight" here) is not considered. We need to distribute this weight properly. However, without value profiling, we have no idea how to distribute it. In this patch, I applied the heuristic that this weight is evenly distributed to successors. For example, given a switch statement with cases 1,2,3,5,10,11,20, and every edge from switch to each successor has weight 10. If there is a binary search tree built to test if n < 10, then its two out-edges will have weight 4x10+10/2 = 45 and 3x10 + 10/2 = 35 respectively (currently they are 40 and 30 without considering the default weight). Each distribution (which is 5 here) will be stored in each SwitchWorkListItem for further distribution. There are some exceptions: For a jump table header which doesn't have any edge to default statement, we don't distribute the default weight to it. For a bit test header which covers a contiguous range and hence has no edges to default statement, we don't distribute the default weight to it. When the branch checks a single value or a contiguous range with no edge to default statement, we don't distribute the default weight to it. In other cases, the default weight is evenly distributed to successors. Differential Revision: http://reviews.llvm.org/D12418 llvm-svn: 246522
* LTO: Cleanup parameter names and header docs, NFCDuncan P. N. Exon Smith2015-08-311-53/+48
| | | | | | | | Follow LLVM style for the parameter names (`CamelCase` not `camelCase`), and surface the header docs in doxygen. No functionality change intended. llvm-svn: 246509
* [DAGCombine] Fixup SETCC legality checkingHal Finkel2015-08-311-11/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | SETCC is one of those special node types for which operation actions (legality, etc.) is keyed off of an operand type, not the node's value type. This makes sense because the value type of a legal SETCC node is determined by its operands' value type (via the TLI function getSetCCResultType). When the SDAGBuilder creates SETCC nodes, it either creates them with an MVT::i1 value type, or directly with the value type provided by TLI.getSetCCResultType. The first problem being fixed here is that DAGCombine had several places querying TLI.isOperationLegal on SETCC, but providing the return of getSetCCResultType, instead of the operand type directly. This does not mean what the author thought, and "luckily", most in-tree targets have SETCC with Custom lowering, instead of marking them Legal, so these checks return false anyway. The second problem being fixed here is that two of the DAGCombines could create SETCC nodes with arbitrary (integer) value types; specifically, those that would simplify: (setcc a, b, op1) and|or (setcc a, b, op2) -> setcc a, b, op3 (which is possible for some combinations of (op1, op2)) If the operands of the and|or node are actual setcc nodes, then this is not an issue (because the and|or must share the same type), but, the relevant code in DAGCombiner::visitANDLike and DAGCombiner::visitORLike actually calls DAGCombiner::isSetCCEquivalent on each operand, and that function will recognise setcc-like select_cc nodes with other return types. And, thus, when creating new SETCC nodes, we need to be careful to respect the value-type constraint. This is even true before type legalization, because it is quite possible for the SELECT_CC node to have a legal type that does not happen to match the corresponding TLI.getSetCCResultType type. To be explicit, there is nothing that later fixes the value types of SETCC nodes (if the type is legal, but does not happen to match TLI.getSetCCResultType). Creating SETCCs with an MVT::i1 value type seems to work only because, either MVT::i1 is not legal, or it is what TLI.getSetCCResultType returns if it is legal. Fixing that is a larger change, however. For the time being, restrict the relevant transformations to produce only SETCC nodes with a value type matching TLI.getSetCCResultType (or MVT::i1 prior to type legalization). Fixes PR24636. llvm-svn: 246507
* don't set a legal vector type if we know we can't use that type (NFCI)Sanjay Patel2015-08-311-18/+12
| | | | | | Added benefit: the 'if' logic now matches the text of the comment that describes it. llvm-svn: 246506
* [BasicAA] Fix the handling of sext and zext in the analysis of GEPs.Quentin Colombet2015-08-311-48/+215
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Hopefully this will end the GEPs saga! This commit reverts r245394, i.e., it reapplies r221876 while incorporating the fixes from D11847. r221876 was not reapplied alone because it was not safe and D11847 was not applied alone because it needs r221876 to produce correct results. This should fix PR24596. Original commit message for r221876: Let's try this again... This reverts r219432, plus a bug fix. Description of the bug in r219432 (by Nick): The bug was using AllPositive to break out of the loop; if the loop break condition i != e is changed to i != e && AllPositive then the test_modulo_analysis_with_global test I've added will fail as the Modulo will be calculated incorrectly (as the last loop iteration is skipped, so Modulo isn't updated with its Scale). Nick also adds this comment: ComputeSignBit is safe to use in loops as it takes into account phi nodes, and the == EK_ZeroEx check is safe in loops as, no matter how the variable changes between iterations, zero-extensions will always guarantee a zero sign bit. The isValueEqualInPotentialCycles check is therefore definitely not needed as all the variable analysis holds no matter how the variables change between loop iterations. And this patch also adds another enhancement to GetLinearExpression - basically to convert ConstantInts to Offsets (see test_const_eval and test_const_eval_scaled for the situations this improves). Original commit message: This reverts r218944, which reverted r218714, plus a bug fix. Description of the bug in r218714 (by Nick): The original patch forgot to check if the Scale in VariableGEPIndex flipped the sign of the variable. The BasicAA pass iterates over the instructions in the order they appear in the function, and so BasicAliasAnalysis::aliasGEP is called with the variable it first comes across as parameter GEP1. Adding a %reorder label puts the definition of %a after %b so aliasGEP is called with %b as the first parameter and %a as the second. aliasGEP later calculates that %a == %b + 1 - %idxprom where %idxprom >= 0 (if %a was passed as the first parameter it would calculate %b == %a - 1 + %idxprom where %idxprom >= 0) - ignoring that %idxprom is scaled by -1 here lead the patch to incorrectly conclude that %a > %b. Revised patch by Nick White, thanks! Thanks to Lang to isolating the bug. Slightly modified by me to add an early exit from the loop and avoid unnecessary, but expensive, function calls. Original commit message: Two related things: 1. Fixes a bug when calculating the offset in GetLinearExpression. The code previously used zext to extend the offset, so negative offsets were converted to large positive ones. 2. Enhance aliasGEP to deduce that, if the difference between two GEP allocations is positive and all the variables that govern the offset are also positive (i.e. the offset is strictly after the higher base pointer), then locations that fit in the gap between the two base pointers are NoAlias. Patch by Nick White! Message from D11847: Un-revert of r241981 and fix for PR23626. The 'Or' case of GetLinearExpression delegates to 'Add' if possible, and if not it returns an Opaque value. Unfortunately the Scale and Offsets weren't being set (and so defaulted to 0) - and a scale of zero effectively removes the variable from the GEP instruction. This meant that BasicAA would return MustAliases when it should have been returning PartialAliases (and PR23626 was an example of the GVN pass using an incorrect MustAlias to merge loads from what should have been different pointers). Differential Revision: http://reviews.llvm.org/D11847 Patch by Nick White <n.j.white@gmail.com>! llvm-svn: 246502
* WebAssembly: generate load/storeJF Bastien2015-08-313-49/+113
| | | | | | | | | Summary: This handles all load/store operations that WebAssembly defines, and handles those necessary for C++ such as i1. I left a FIXME for outstanding features which aren't required for now. Reviewers: sunfish Subscribers: jfb, llvm-commits, dschuff llvm-svn: 246500
* generalize helper function of MergeConsecutiveStores to handle vector types ↵Sanjay Patel2015-08-311-14/+21
| | | | | | | | | | (NFCI) This was part of D7208 (r227242), but that commit was reverted because it exposed a bug in AArch64 lowering. I should have that fixed and the rest of the commit reinstated soon. llvm-svn: 246493
* Fix bug in method LLLexer::FP80HexToIntPairKarl Schimpf2015-08-311-1/+1
| | | | llvm-svn: 246489
* Fix Windows build by including raw_ostream.hHans Wennborg2015-08-311-0/+1
| | | | llvm-svn: 246486
* Rollback of commit "Repress sanitization on User dtor."Naomi Musgrave2015-08-312-6/+2
| | | | | | | | | | | This would have suppressed bug 24578, about use-after- destroy on User and MDNode. Rolled back suppression for the sake of code cleanliness, in preferance for bug tracking to keep track of this issue. This reverts commit 6ff2baabc4625d5b0a8dccf76aa0f72d930ea6c0. llvm-svn: 246484
* [DAGCombine] Use getSetCCResultType utility functionHal Finkel2015-08-311-1/+1
| | | | | | | DAGCombine has a utility wrapper around TLI's getSetCCResultType; use it in the one place in DAGCombine still directly calling the TLI function. NFC. llvm-svn: 246482
* [x86] enable machine combiner reassociations for scalar 'or' instsSanjay Patel2015-08-311-0/+4
| | | | llvm-svn: 246481
* [EH] Handle non-Function personalities like unknown personalitiesReid Kleckner2015-08-317-82/+22
| | | | | | | | | Also delete and simplify a lot of MachineModuleInfo code that used to be needed to handle personalities on landingpads. Now that the personality is on the LLVM Function, we no longer need to track it this way on MMI. Certainly it should not live on LandingPadInfo. llvm-svn: 246478
* [FunctionAttr] Infer nonnull attributes on returnsPhilip Reames2015-08-311-0/+148
| | | | | | | | Teach FunctionAttr to infer the nonnull attribute on return values of functions which never return a potentially null value. This is done both via a conservative local analysis for the function itself and a optimistic per-SCC analysis. If no function in the SCC returns anything which could be null (other than values from other functions in the SCC), we can conclude no function returned a null pointer. Even if some function within the SCC returns a null pointer, we may be able to locally conclude that some don't. Differential Revision: http://reviews.llvm.org/D9688 llvm-svn: 246476
* [AArch64][CollectLOH] Remove an invalid assertion and add a test case ↵Quentin Colombet2015-08-311-3/+11
| | | | | | | | exposing it. rdar://problem/22491525 llvm-svn: 246472
* Undo reversion on commit: Revert "Revert "Repress sanitization on User dtor.Naomi Musgrave2015-08-312-2/+6
| | | | | | | | Modify msan macros for applying attribute"" This reverts commit 020e70a79878c96457e6882bcdfaf6628baf32b7. llvm-svn: 246470
* [DAGCombine] Remove some old dead code for forming SETCC nodesHal Finkel2015-08-311-45/+0
| | | | | | | | | | This code was dead when it was committed in r23665 (Oct 7, 2005), and before it reaches its 10th anniversary, it really should go. We can always bring it back if we'd like, but it forms more SETCC nodes, and the way we do legality checking on SETCC nodes is wrong in a number of places, and removing this means fewer places to fix. NFC. llvm-svn: 246466
* [LazyValueInfo] Look through Phi nodes when trying to prove a predicatePhilip Reames2015-08-311-5/+35
| | | | | | | | | | | | | | | | | | If asked to prove a predicate about a value produced by a PHI node, LazyValueInfo was unable to do so even if the predicate was known to be true for each input to the PHI. This prevented JumpThreading from eliminating a provably redundant branch. The problematic test case looks something like this: ListNode *p = ...; while (p != null) { if (!p) return; x = g->x; // unrelated p = p->next } The null check at the top of the loop is redundant since the value of 'p' is null checked on entry to the loop and before executing the backedge. This resulted in us a) executing an extra null check per iteration and b) not being able to LICM unrelated loads after the check since we couldn't prove they would execute or that their dereferenceability wasn't effected by the null check on the first iteration. Differential Revision: http://reviews.llvm.org/D12383 llvm-svn: 246465
* Rework of the new interface for shrink wrappingKit Barton2015-08-312-21/+29
| | | | | | | | | | | | | | | Based on comments from Hal (http://lists.llvm.org/pipermail/llvm-commits/Week-of-Mon-20150810/292978.html), I've changed the interface to add a callback mechanism to the TargetFrameLowering class to query whether the specific target supports shrink wrapping. By default, shrink wrapping is disabled by default. Each target can override the default behaviour using the TargetFrameLowering::targetSupportsShrinkWrapping() method. Shrink wrapping can still be explicitly enabled or disabled from the command line, using the existing -enable-shrink-wrap=<true|false> option. Phabricator: http://reviews.llvm.org/D12293 llvm-svn: 246463
* AArch64: Fix loads to lower NEON vector lanes using GPR registersMatthias Braun2015-08-311-1/+4
| | | | | | | | | | | | | The ISelLowering code turned insertion turned the element for the lowest lane of a BUILD_VECTOR into an INSERT_SUBREG, this prohibited the patterns for SCALAR_TO_VECTOR(Load) to match later. Restrict this to cases without a load argument. Reported in rdar://22223823 Differential Revision: http://reviews.llvm.org/D12467 llvm-svn: 246462
* X86: Fix FastISel SSESelect register classMatthias Braun2015-08-311-3/+9
| | | | | | | | | X86FastISel has been using the wrong register class for VBLENDVPS which produces a VR128 and needs an extra copy to the target register. The problem was already hit by the existing test cases when using > llvm-lit -Dllc="llc -verify-machineinstr" llvm-svn: 246461
* [BitcodeReader] Ensure we can read constant vector selects with an i1 conditionFilipe Cabecinhas2015-08-311-4/+5
| | | | | | | | | | | | | | | Summary: Constant vectors weren't allowed to have an i1 condition in the BitcodeReader. Make sure we have the same restrictions that are documented, not more. Reviewers: nlewycky, rafael, kschimpf Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D12440 llvm-svn: 246459
* [MC/AsmParser] Avoid setting MCSymbol.IsUsed in some casesVedant Kumar2015-08-311-9/+8
| | | | | | | | | | | | | | | | | | | | Avoid marking some MCSymbols as used in MC/AsmParser.cpp when no uses exist. This fixes a bug in parseAssignmentExpression() which inadvertently sets IsUsed, thereby triggering: "invalid re-assignment of non-absolute variable" on otherwise valid code. No other functionality change intended. The original version of this patch touched many calls to MCSymbol accessors. On rafael's advice, I have stripped this patch down a bit. As a follow-up, I intend to find the call sites which intentionally set IsUsed and force them to do so explicitly. Differential Revision: http://reviews.llvm.org/D12347 llvm-svn: 246457
* Change comment to verify commit accesss.Karl Schimpf2015-08-311-1/+1
| | | | llvm-svn: 246451
* Revert "Repress sanitization on User dtor. Modify msan macros for applying ↵Naomi Musgrave2015-08-312-6/+2
| | | | | | | | attribute" This reverts commit 5e3bfbb38eb3fb6f568b107f6b239e0aa4c5f334. llvm-svn: 246450
* Repress sanitization on User dtor. Modify msan macros for applying attributeNaomi Musgrave2015-08-312-2/+6
| | | | | | | | | | | | | | | to repress sanitization. Move attribute for repressing sanitization to operator delete for User, MDNode. Summary: In response to bug 24578, reported against failing LLVM test. Reviewers: chandlerc, rsmith, eugenis Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D12335 llvm-svn: 246449
* [SectionMemoryManager] Use range-based for loops. No functional change intended.Benjamin Kramer2015-08-311-21/+10
| | | | llvm-svn: 246440
* AVX512: ktest implemantationIgor Breger2015-08-314-14/+16
| | | | | | | | Added tests for encoding. Differential Revision: http://reviews.llvm.org/D11979 llvm-svn: 246439
* AVX512: Implemented encoding and intrinsics for vdbpsadbwIgor Breger2015-08-315-1/+15
| | | | | | | | Added tests for intrinsics and encoding. Differential Revision: http://reviews.llvm.org/D12491 llvm-svn: 246436
* AVX512: kadd implementationIgor Breger2015-08-311-2/+4
| | | | | | | | Added tests for encoding. Differential Revision: http://reviews.llvm.org/D11973 llvm-svn: 246432
* AVX512: Implemented encoding and intrinsics for vpalignrIgor Breger2015-08-314-34/+92
| | | | | | | | Added tests for intrinsics and encoding. Differential Revision: http://reviews.llvm.org/D12270 llvm-svn: 246428
* [AggressiveAntiDepBreaker] Check for EarlyClobber on defining instructionHal Finkel2015-08-311-0/+14
| | | | | | | | | AggressiveAntiDepBreaker was doing some EarlyClobber checking, but was not checking that the register being potentially renamed was defined by an early-clobber def where there was also a use, in that instruction, of the register being considered as the target of the rename. Fixes PR24014. llvm-svn: 246423
* [JumpThreading] make jump threading respect convergent annotation.Jingyue Wu2015-08-311-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: JumpThreading shouldn't duplicate a convergent call, because that would move a convergent call into a control-inequivalent location. For example, if (cond) { ... } else { ... } convergent_call(); if (cond) { ... } else { ... } should not be optimized to if (cond) { ... convergent_call(); ... } else { ... convergent_call(); ... } Test Plan: test/Transforms/JumpThreading/basic.ll Patch by Xuetian Weng. Reviewers: resistor, arsenm, jingyue Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D12484 llvm-svn: 246415
* Support: Support LLVM_ENABLE_THREADS=0 in llvm/Support/thread.h.Peter Collingbourne2015-08-311-2/+2
| | | | | | | | Specifically, the header now provides llvm::thread, which is either a typedef of std::thread or a replacement that calls the function synchronously depending on the value of LLVM_ENABLE_THREADS. llvm-svn: 246402
* [PowerPC] Fixup SELECT_CC (and SETCC) patterns with i1 comparison operandsHal Finkel2015-08-304-5/+168
| | | | | | | | | | | | | | | | | | | | | | There were really two problems here. The first was that we had the truth tables for signed i1 comparisons backward. I imagine these are not very common, but if you have: setcc i1 x, y, LT this has the '0 1' and the '1 0' results flipped compared to: setcc i1 x, y, ULT because, in the signed case, '1 0' is really '-1 0', and the answer is not the same as in the unsigned case. The second problem was that we did not have patterns (at all) for the unsigned comparisons select_cc nodes for i1 comparison operands. This was the specific cause of PR24552. These had to be added (and a missing Altivec promotion added as well) to make sure these function for all types. I've added a bunch more test cases for these patterns, and there are a few FIXMEs in the test case regarding code-quality. Fixes PR24552. llvm-svn: 246400
* NFC: Code style in VectorUtils.cppElena Demikhovsky2015-08-301-10/+12
| | | | | | Differential Revision: http://reviews.llvm.org/D12478 llvm-svn: 246381
* Revert "Revert "New interface function is added to VectorUtils Value ↵Renato Golin2015-08-302-17/+39
| | | | | | | | | *getSplatValue(Value *Val);"" This reverts commit r246379. It seems that the commit was not the culprit, and the bot will be investigated for instability. llvm-svn: 246380
* Revert "New interface function is added to VectorUtils Value ↵Renato Golin2015-08-302-39/+17
| | | | | | | | | | *getSplatValue(Value *Val);" This reverts commit r246371, as it cause a rather obscure bug in AArch64 test-suite paq8p (time outs, seg-faults). I'll investigate it before reapplying. llvm-svn: 246379
* Stop calling the flat out insane ARM target parsing code unless theChandler Carruth2015-08-301-8/+20
| | | | | | | | | | | | | | | | | | | | | | | architecture string is something quite weird. Similarly delay calling the BPF parsing code, although that is more reasonable. To understand why I was motivated to make this change, it cuts the time for running the ADT TripleTest unittests by a factor of two in non-optimized builds (the developer default) and reduces my 'check-llvm' time by a full 15 seconds. The implementation of parseARMArch is *that* slow. I tried to fix it in the prior series of commits, but frankly, I have no idea how to finish fixing it. The entire premise of the function (to allow 'v7a-unknown-linux' or some such to parse as an 'arm-unknown-linux' triple) seems completely insane to me, but I'll let the ARM folks sort that out. At least it is now out of the critical path of every developer working on LLVM. It also will likely make some other folks' code significantly faster as I've heard reports of 2% of time spent in triple parsing even in optimized builds! I'm not done making this code faster, but I am done trying to improve the ARM target parsing code. llvm-svn: 246378
* Remove a linear walk to find the default FPU for a given CPU by directlyChandler Carruth2015-08-301-7/+6
| | | | | | expanding the .def file within a StringSwitch. llvm-svn: 246377
* [MIR Serialization] static -> static const in ↵Hal Finkel2015-08-303-5/+5
| | | | | | | | | getSerializable*MachineOperandTargetFlags Make the arrays 'static const' instead of just 'static'. Post-commit review comment from Roman Divacky on IRC. NFC. llvm-svn: 246376
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