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* [mips][microMIPS] Implement BC16, BEQZC16 and BNEZC16 instructionsZoran Jovanovic2015-09-076-10/+94
| | | | | | Differential Revision: http://reviews.llvm.org/D11181 llvm-svn: 246963
* [ARM] Get rid of SelectT2ShifterOperandReg, NFCJohn Brawn2015-09-072-26/+2
| | | | | | | | | SelectT2ShifterOperandReg has identical behaviour to SelectImmShifterOperand, so get rid of it and use SelectImmShifterOperand instead. Differential Revision: http://reviews.llvm.org/D12195 llvm-svn: 246962
* [mips][microMIPS] Implement CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, ↵Zoran Jovanovic2015-09-074-58/+290
| | | | | | | | MAX.fmt, MIN.fmt, MAXA.fmt, MINA.fmt and CMP.condn.fmt instructions Differential Revision: http://reviews.llvm.org/D12141 llvm-svn: 246960
* Prune utf8 chars in comments.NAKAMURA Takumi2015-09-072-3/+3
| | | | llvm-svn: 246953
* [InstCombine] Don't divide by zero when evaluating a potential transformDavid Majnemer2015-09-061-0/+8
| | | | | | | | | | Trivial multiplication by zero may survive the worklist. We tried to reassociate the multiplication with a division instruction, causing us to divide by zero; bail out instead. This fixes PR24726. llvm-svn: 246939
* [SelectionDAG] Swap commutative binops before constant-based foldingHal Finkel2015-09-061-6/+7
| | | | | | | | | | | | | | | | | In searching for a fix for the underlying code-quality bug highlighted by r246937 (that SDAG simplification can lead to us generating an ISD::OR node with a constant zero LHS), I ran across this: We generically canonicalize commutative binary-operation nodes in SDAG getNode so that, if only one operand is a constant, it will be on the RHS. However, we were doing this only after a bunch of constant-based simplification checks that all assume this canonical form (that any constant will be on the RHS). Moving the operand-swapping canonicalization prior to these checks seems like the right thing to do (and, as it turns out, causes SDAG to completely fold away the computation in test/CodeGen/ARM/2012-11-14-subs_carry.ll, just like InstCombine would do). llvm-svn: 246938
* [PowerPC] Don't commute trivial rlwimi instructionsHal Finkel2015-09-061-0/+5
| | | | | | | | | | | | | | | To commute a trivial rlwimi instructions (meaning one with a full mask and zero shift), we'd need to ability to form an all-zero mask (instead of an all-one mask) using rlwimi. We can't represent this, however, and we'll miscompile code if we try. The code quality problem that this highlights (that SDAG simplification can lead to us generating an ISD::OR node with a constant zero LHS) will be fixed as a follow-up. Fixes PR24719. llvm-svn: 246937
* [InstCombine] Don't assume m_Mul gives back an InstructionDavid Majnemer2015-09-051-1/+3
| | | | | | This fixes PR24713. llvm-svn: 246933
* Added arch extensions and default target features in TargetParser.Alexandros Lamprineas2015-09-051-5/+30
| | | | | Differential: http://reviews.llvm.org/D11590 llvm-svn: 246930
* [mips][microMIPS] Implement ADD.fmt, SUB.fmt, MOV.fmt, MUL.fmt, DIV.fmt, ↵Zoran Jovanovic2015-09-053-4/+159
| | | | | | | | MADDF.fmt, MSUBF.fmt and NEG.fmt instructions Differential Revision: http://reviews.llvm.org/D11978 llvm-svn: 246919
* Fix build warning.Craig Topper2015-09-051-1/+1
| | | | llvm-svn: 246908
* WinCOFFObjectWriter.cpp: Roll back TimeDateStamp along ENABLE_TIMESTAMPS.NAKAMURA Takumi2015-09-051-0/+5
| | | | | | | We want a deterministic output. GNU AS leaves it zero. FIXME: It may be optional by its user, like llc and clang. llvm-svn: 246905
* Fix build warningAndrew Kaylor2015-09-051-2/+2
| | | | llvm-svn: 246903
* [PowerPC] Fix and(or(x, c1), c2) -> rlwimi generationHal Finkel2015-09-051-3/+15
| | | | | | | | | | | | | | | | PPCISelDAGToDAG has a transformation that generates a rlwimi instruction from an input pattern that looks like this: and(or(x, c1), c2) but the associated logic does not work if there are bits that are 1 in c1 but 0 in c2 (these are normally canonicalized away, but that can't happen if the 'or' has other users. Make sure we abort the transformation if such bits are discovered. Fixes PR24704. llvm-svn: 246900
* Fix build warningAndrew Kaylor2015-09-041-4/+0
| | | | llvm-svn: 246899
* [WinEH] Teach SimplfyCFG to eliminate empty cleanup pads.Andrew Kaylor2015-09-041-20/+201
| | | | | | Differential Revision: http://reviews.llvm.org/D12434 llvm-svn: 246896
* [libFuzzer] more accurate logic for traces, 80-char fixKostya Serebryany2015-09-041-6/+5
| | | | llvm-svn: 246888
* Remove two unused includes and C++11 rangify for loops.Yaron Keren2015-09-041-15/+12
| | | | llvm-svn: 246865
* Typo. NFC.Chad Rosier2015-09-041-1/+1
| | | | llvm-svn: 246851
* [MC] Replace comparison with isUInt<32>.David Majnemer2015-09-041-1/+1
| | | | | | | Casting to unsigned long can cause the time to get truncated to 32-bits, making it appear to be a valid timestamp. Just use isUInt<32> instead. llvm-svn: 246840
* WinCOFFObjectWriter.cpp: Appease a warning in checking std::time_t. ↵NAKAMURA Takumi2015-09-041-1/+1
| | | | | | [-Wsign-compare] llvm-svn: 246839
* [libFuzzer] when a single mutation fails try a few more times with other ↵Kostya Serebryany2015-09-041-7/+14
| | | | | | mutations before returning un-mutated data llvm-svn: 246828
* [libFuzzer] actually make the dictionaries work (+docs)Kostya Serebryany2015-09-049-24/+170
| | | | llvm-svn: 246825
* [PowerPC] Enable interleaved-access vectorizationHal Finkel2015-09-042-1/+43
| | | | | | | | | | | This adds a basic cost model for interleaved-access vectorization (and a better default for shuffles), and enables interleaved-access vectorization by default. The relevant difference from the default cost model for interleaved-access vectorization, is that on PPC, the shuffles that end up being used are *much* cheaper than modeling the process with insert/extract pairs (which are quite expensive, especially on older cores). llvm-svn: 246824
* [PowerPC] Always use aggressive interleaving on the A2Hal Finkel2015-09-031-0/+7
| | | | | | | | On the A2, with an eye toward QPX unaligned-load merging, we should always use aggressive interleaving. It is generally superior to only using concatenation unrolling. llvm-svn: 246819
* [PowerPC] Try harder to find a base+offset when looking for consecutive accessesHal Finkel2015-09-031-7/+23
| | | | | | | | | | | | | | | | | | When forming permutation-based unaligned vector loads, we need to know whether it is valid to read ahead of the requested address by a full vector length. Doing so is more efficient (and allows for more CSE with later loads), but could trigger a page fault if invalid. To determine validity, we look for other loads in the same block that access the relevant address range. The relevant point here is that we need to do this as part of the process of forming permutation-based vector loads, and this happens quite early in the SDAG pipeline - specifically before many of the address calculations are fully canonicalized. As a result, we need to try harder to recognize base+offset address computations, because they still might appear as chain of adds (base+offset+offset, for example). To account for this, we'll look through chains of adds, accumulating the constant offsets. llvm-svn: 246813
* [IR] Have AttrBuilder::clear clear `TargetDepAttrs`.Sanjoy Das2015-09-031-0/+1
| | | | | | | Test case attached -- currently the parser smears the "foo bar" to all of the formal arguments. llvm-svn: 246812
* [RewriteStatepointsForGC] Extract common code, comment, and fix a build ↵Philip Reames2015-09-031-55/+48
| | | | | | warning [NFC] llvm-svn: 246810
* [RewriteStatepointsForGC] Strengthen invariants around BDVsPhilip Reames2015-09-031-29/+65
| | | | | | | | | | As a first step towards a new implementation of the base pointer inference algorithm, introduce an abstraction for BDVs, strengthen the assertions around them, and rewrite the BDV relation code in terms of the abstraction which includes an explicit notion of whether the BDV is also a base. The later is motivated by the fact we had a bug where insertelement was always assumed to be a base pointer even though the BDV code knew it wasn't. The strengthened assertions in this patch would have caught that bug. The next step will be to separate the DefiningValueMap into a BDV use list cache (entirely within findBasePointers) and a base pointer cache. Having the former will allow me to use a deterministic visit order when visiting BDVs in the inference algorithm and remove a bunch of ordering related hacks. Before actually doing the last step, I'm likely going to extend the lattice with a 'BaseN' (seen only base inputs) state so that I can kill the post process optimization step. Phabricator Revision: http://reviews.llvm.org/D12608 llvm-svn: 246809
* [libFuzzer] refactor the mutation functions so that they are now methods of ↵Kostya Serebryany2015-09-035-69/+80
| | | | | | a class. NFC llvm-svn: 246808
* [PowerPC] Include the permutation cost for unaligned vector loadsHal Finkel2015-09-031-8/+12
| | | | | | | | | | Pre-P8, when we generate code for unaligned vector loads (for Altivec and QPX types), even when accounting for the combining that takes place for multiple consecutive such loads, there is at least one load instructions and one permutation for each load. Make sure the cost reported reflects the cost of the permutes as well. llvm-svn: 246807
* [PowerPC] Compute the MMO offset for an unaligned load with signed arithmeticHal Finkel2015-09-031-1/+2
| | | | | | | | | | | If you compute the MMO offset using unsigned arithmetic, you end up with a large positive offset instead of a small negative one. In theory, this could cause bad instruction-scheduling decisions later. I noticed this by inspection from the debug output, and using that for the regression test is the best I can do right now. llvm-svn: 246805
* [RewriteStatepointsForGC] Workaround a lack of determinism in visit orderPhilip Reames2015-09-031-4/+9
| | | | | | | | The visit order being used in the base pointer inference algorithm is currently non-deterministic. When working on http://reviews.llvm.org/D12583, I discovered that we were relying on a peephole optimization to get deterministic ordering in one of the test cases. This change is intented to let me test and land http://reviews.llvm.org/D12583. The current code will not be long lived. I'm starting to investigate a rewrite of the algorithm which will combine the post-process step into the initial algorithm and make the visit order determistic. Before doing that, I wanted to make sure the existing code was complete and the test were stable. Hopefully, patches should be up for review for the new algorithm this week or early next. llvm-svn: 246801
* [libFuzzer] adding a parser for AFL-style dictionaries + tests.Kostya Serebryany2015-09-035-0/+141
| | | | llvm-svn: 246800
* [sancov] Disable sanitizer coverage on functions using SEHReid Kleckner2015-09-031-0/+7
| | | | | | | Splitting basic blocks really messes up WinEHPrepare. We can remove this change when SEH uses the new EH IR. llvm-svn: 246799
* [AArch64] Improve ISel using across lane addition reduction.Chad Rosier2015-09-031-0/+99
| | | | | | | | | | | | | | | | | | | | In vectorized add reduction code, the final "reduce" step is sub-optimal. This change wll combine : ext v1.16b, v0.16b, v0.16b, #8 add v0.4s, v1.4s, v0.4s dup v1.4s, v0.s[1] add v0.4s, v1.4s, v0.4s into addv s0, v0.4s PR21371 http://reviews.llvm.org/D12325 Patch by Jun Bum Lim <junbuml@codeaurora.org>! llvm-svn: 246790
* Allow global address space forward decls using IDs in .ll files.Karl Schimpf2015-09-031-16/+13
| | | | | | | | | | Summary: This fixes bugzilla bug 24656. Fixes the case where there is a forward reference to a global variable using an ID (i.e. @0). It does this by passing the address space of the initializer pointer for which the forward referenced global is used. llvm-svn: 246788
* Sink COFF.h MC include into .cpp filesReid Kleckner2015-09-035-0/+5
| | | | | | | | This prevents MC clients from getting COFF.h, which conflicts with winnt.h macros. Also a minor IWYU cleanup. Now the only public headers including COFF.h are in Object, and they actually need it. llvm-svn: 246784
* Revert "[AArch64] Improve load/store optimizer to handle LDUR + LDR."Chad Rosier2015-09-031-77/+21
| | | | | | | | This reverts commit r246769. This appears to have broken Multisource/Benchmarks/tramp3d-v4. llvm-svn: 246782
* [x86] enable machine combiner reassociations for scalar 'xor' instsSanjay Patel2015-09-031-0/+4
| | | | llvm-svn: 246781
* Fix assertion failure in LLParser::ConvertValIDToValueKarl Schimpf2015-09-032-3/+2
| | | | | | | | | | | Summary: Fixes bug 24645. Problem appears to be that the type may be undefined when ConvertValIDToValue is called. Reviewers: kcc Subscribers: llvm-commits llvm-svn: 246779
* Fix SEGV in InlineAsm::ConstraintInfo::Parse.Karl Schimpf2015-09-031-1/+2
| | | | | | | | | | | | | Summary: Fixes bug 24646. Previous code was not checking if an index into a vector was valid, resulting in a SEGV. Fixed by assuming the construct can't be parsed when given this input. Reformat and add test. Differential Revision: http://reviews.llvm.org/D12539 llvm-svn: 246774
* Fix SEGV in InlineAsm::ConstraintInfo::Parse.Karl Schimpf2015-09-031-1/+2
| | | | | | | | Fixes bug 24646. Previous code was not checking if an index into a vector was valid, resulting in a SEGV. Fixed by assuming the construct can't be parsed when given this input. llvm-svn: 246773
* check for fastness before merging in DAGCombiner::MergeConsecutiveStores() Sanjay Patel2015-09-032-12/+20
| | | | | | | | | | | | | | | | Use and check the 'IsFast' optional parameter to TLI.allowsMemoryAccess() any time we have a merged access candidate. Without this patch, we were generating unaligned 16-byte (SSE) memops for x86 targets where those accesses are slow. This change was mentioned in: http://reviews.llvm.org/D10662 and http://reviews.llvm.org/D10905 and will help solve PR21711. Differential Revision: http://reviews.llvm.org/D12573 llvm-svn: 246771
* [AArch64] Improve load/store optimizer to handle LDUR + LDR.Chad Rosier2015-09-031-21/+77
| | | | | | | | | | | This patch allows the mixing of scaled and unscaled load/stores to form load/store pairs. PR24465 http://reviews.llvm.org/D12116 Many thanks to Ahmed and Michael for fixes and code review. llvm-svn: 246769
* [AArch64] Reuse MayLoad. NFC.Chad Rosier2015-09-031-1/+1
| | | | llvm-svn: 246767
* [mips] Added support for the div, divu, ddiv and ddivu macros which use ↵Daniel Sanders2015-09-035-1/+182
| | | | | | | | | | | | | | | | traps and breaks in the integrated assembler. Summary: Patch by Scott Egerton Reviewers: vkalintiris, dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D11675 llvm-svn: 246763
* [WinEH] Add llvm.eh.exceptionpointer intrinsicJoseph Tremoulet2015-09-031-0/+5
| | | | | | | | | | | | | | | | | Summary: This intrinsic can be used to extract a pointer to the exception caught by a given catchpad. Its argument has token type and must be a `catchpad`. Also clarify ExtendingLLVM documentation regarding overloaded intrinsics. Reviewers: majnemer, andrew.w.kaylor, sanjoy, rnk Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D12533 llvm-svn: 246752
* [WinEH] Add cleanupendpad instructionJoseph Tremoulet2015-09-0317-19/+223
| | | | | | | | | | | | | | | | | | | | | | | Summary: Add a `cleanupendpad` instruction, used to mark exceptional exits out of cleanups (for languages/targets that can abort a cleanup with another exception). The `cleanupendpad` instruction is similar to the `catchendpad` instruction in that it is an EH pad which is the target of unwind edges in the handler and which itself has an unwind edge to the next EH action. The `cleanupendpad` instruction, similar to `cleanupret` has a `cleanuppad` argument indicating which cleanup it exits. The unwind successors of a `cleanuppad`'s `cleanupendpad`s must agree with each other and with its `cleanupret`s. Update WinEHPrepare (and docs/tests) to accomodate `cleanupendpad`. Reviewers: rnk, andrew.w.kaylor, majnemer Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D12433 llvm-svn: 246751
* AVX512: Implemented encoding and intrinsics for vplzcntq, vplzcntd, ↵Igor Breger2015-09-035-117/+54
| | | | | | | | | | vpconflictq, vpconflictd Added tests for intrinsics and encoding. Differential Revision: http://reviews.llvm.org/D11931 llvm-svn: 246750
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