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* [AMDGPU] Support for "uniform-work-group-size" attributeAakanksha Patil2018-12-122-7/+65
| | | | | | | | Updated the annotate-kernel-features pass to support the propagation of uniform-work-group attribute from the kernel to the called functions. Once this pass is run, all kernels, even the ones which initially did not have the attribute, will be able to indicate weather or not they have uniform work group size depending on the value of the attribute. Differential Revision: https://reviews.llvm.org/D50200 llvm-svn: 348971
* DebugInfo/DWARF: Pretty print subroutine typesDavid Blaikie2018-12-121-2/+19
| | | | | | | | Doesn't handle varargs and other fun things, but it's a start. (also doesn't print these strictly as valid C++ when it's a pointer to function, it'll print as "void(int)*" instead of "void (*)(int)") llvm-svn: 348965
* [AMDGPU] Emit MessagePack HSA Metadata for v3 code objectScott Linder2018-12-1212-142/+1156
| | | | | | | | | Continue to present HSA metadata as YAML in ASM and when output by tools (e.g. llvm-readobj), but encode it in Messagepack in the code object. Differential Revision: https://reviews.llvm.org/D48179 llvm-svn: 348963
* DebugInfo/DWARF: Improve dumping of pointers to members ('int foo::*' rather ↵David Blaikie2018-12-121-0/+5
| | | | | | than 'int*') llvm-svn: 348962
* DebugInfo/DWARF: Refactor type dumping to dump types, rather than DIEs that ↵David Blaikie2018-12-121-5/+3
| | | | | | | | | | | | reference types This lays the foundation for dumping types not referenced by DW_AT_type attributes (in the near-term, that'll be DW_AT_containing_type for a DW_TAG_ptr_to_member_type - in the future, potentially dumping the pretty printed name next to the DW_TAG for the type, rather than only when the type is referenced from elsewhere) llvm-svn: 348961
* DebugInfo/DWARF: Refactor getAttributeValueAsReferencedDie to accept a ↵David Blaikie2018-12-121-3/+11
| | | | | | | | | DWARFFormValue Save searching for the attribute again when you already have the DWARFFormValue at hand. llvm-svn: 348960
* [X86] Emit SBB instead of SETCC_CARRY from LowerSELECT. Break false ↵Craig Topper2018-12-122-8/+22
| | | | | | | | | | | | dependency on the SBB input. I'm hoping we can just replace SETCC_CARRY with SBB. This is another step towards that. I've explicitly used zero as the input to the setcc to avoid a false dependency that we've had with the SETCC_CARRY. I changed one of the patterns that used NEG to instead use an explicit compare with 0 on the LHS. We needed the zero anyway to avoid the false dependency. The negate would clobber its input register. By using a CMP we can avoid that which could be useful. Differential Revision: https://reviews.llvm.org/D55414 llvm-svn: 348959
* [ConstantFold] Use getMinSignedBits for APInt in isIndexInRangeOfArrayType.Florian Hahn2018-12-121-1/+1
| | | | | | | | | | | | | | | | | Indices for getelementptr can be signed so we should use getMinSignedBits instead of getActiveBits here. The function later calls getSExtValue to get the int64_t value, which also checks getMinSignedBits. This fixes https://bugs.chromium.org/p/oss-fuzz/issues/detail?id=11647. Reviewers: mssimpso, efriedma, davide Reviewed By: efriedma Differential Revision: https://reviews.llvm.org/D55536 llvm-svn: 348957
* llvm-dwarfdump: Dump array dimensions in stringified type namesDavid Blaikie2018-12-121-2/+21
| | | | llvm-svn: 348954
* [SelectionDAG] Add a generic isSplatValue functionSimon Pilgrim2018-12-123-50/+114
| | | | | | | | | | | | | | This patch introduces a generic function to determine whether a given vector type is known to be a splat value for the specified demanded elements, recursing up the DAG looking for BUILD_VECTOR or VECTOR_SHUFFLE splat patterns. It also keeps track of the elements that are known to be UNDEF - it returns true if all the demanded elements are UNDEF (as this may be useful under some circumstances), so this needs to be handled by the caller. A wrapper variant is also provided that doesn't take the DemandedElts or UndefElts arguments for cases where we just want to know if the SDValue is a splat or not (with/without UNDEFS). I had hoped to completely remove the X86 local version of this function, but I'm seeing some regressions in shift/rotate codegen that will take a little longer to fix and I hope to get this in sooner so I can continue work on PR38243 which needs more capable splat detection. Differential Revision: https://reviews.llvm.org/D55426 llvm-svn: 348953
* [NVPTX] do not rely on cached subtarget info.Artem Belevich2018-12-122-13/+14
| | | | | | | | | | | | | | If a module has function references, but no functions themselves, we may end up never calling runOnMachineFunction and therefore would never initialize nvptxSubtarget field which would eventually cause a crash. Instead of relying on nvptxSubtarget being initialized by one of the methods, retrieve subtarget info directly. Differential Revision: https://reviews.llvm.org/D55580 llvm-svn: 348952
* [x86] allow 8-bit adds to be promoted by convertToThreeAddress() to form LEASanjay Patel2018-12-123-12/+23
| | | | | | | | | | This extends the code that handles 16-bit add promotion to form LEA to also allow 8-bit adds. That allows us to combine add ops with register moves and save some instructions. This is another step towards allowing add truncation in generic DAGCombiner (see D54640). Differential Revision: https://reviews.llvm.org/D55494 llvm-svn: 348946
* [Unroll/UnrollAndJam/Vectorizer/Distribute] Add followup loop attributes.Michael Kruse2018-12-1216-94/+643
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When multiple loop transformation are defined in a loop's metadata, their order of execution is defined by the order of their respective passes in the pass pipeline. For instance, e.g. #pragma clang loop unroll_and_jam(enable) #pragma clang loop distribute(enable) is the same as #pragma clang loop distribute(enable) #pragma clang loop unroll_and_jam(enable) and will try to loop-distribute before Unroll-And-Jam because the LoopDistribute pass is scheduled after UnrollAndJam pass. UnrollAndJamPass only supports one inner loop, i.e. it will necessarily fail after loop distribution. It is not possible to specify another execution order. Also,t the order of passes in the pipeline is subject to change between versions of LLVM, optimization options and which pass manager is used. This patch adds 'followup' attributes to various loop transformation passes. These attributes define which attributes the resulting loop of a transformation should have. For instance, !0 = !{!0, !1, !2} !1 = !{!"llvm.loop.unroll_and_jam.enable"} !2 = !{!"llvm.loop.unroll_and_jam.followup_inner", !3} !3 = !{!"llvm.loop.distribute.enable"} defines a loop ID (!0) to be unrolled-and-jammed (!1) and then the attribute !3 to be added to the jammed inner loop, which contains the instruction to distribute the inner loop. Currently, in both pass managers, pass execution is in a fixed order and UnrollAndJamPass will not execute again after LoopDistribute. We hope to fix this in the future by allowing pass managers to run passes until a fixpoint is reached, use Polly to perform these transformations, or add a loop transformation pass which takes the order issue into account. For mandatory/forced transformations (e.g. by having been declared by #pragma omp simd), the user must be notified when a transformation could not be performed. It is not possible that the responsible pass emits such a warning because the transformation might be 'hidden' in a followup attribute when it is executed, or it is not present in the pipeline at all. For this reason, this patche introduces a WarnMissedTransformations pass, to warn about orphaned transformations. Since this changes the user-visible diagnostic message when a transformation is applied, two test cases in the clang repository need to be updated. To ensure that no other transformation is executed before the intended one, the attribute `llvm.loop.disable_nonforced` can be added which should disable transformation heuristics before the intended transformation is applied. E.g. it would be surprising if a loop is distributed before a #pragma unroll_and_jam is applied. With more supported code transformations (loop fusion, interchange, stripmining, offloading, etc.), transformations can be used as building blocks for more complex transformations (e.g. stripmining+stripmining+interchange -> tiling). Reviewed By: hfinkel, dmgreen Differential Revision: https://reviews.llvm.org/D49281 Differential Revision: https://reviews.llvm.org/D55288 llvm-svn: 348944
* [SampleFDO] Extend profile-sample-accurate option to cover ↵Wei Mi2018-12-121-1/+8
| | | | | | | | | | | | | | isFunctionColdInCallGraph For SampleFDO, when a callsite doesn't appear in the profile, it will not be marked as cold callsite unless the option -profile-sample-accurate is specified. But profile-sample-accurate doesn't cover function isFunctionColdInCallGraph which is used to decide whether a function should be put into text.unlikely section, so even if the user knows the profile is accurate and specifies profile-sample-accurate, those functions not appearing in the sample profile are still not be put into text.unlikely section right now. The patch fixes that. Differential Revision: https://reviews.llvm.org/D55567 llvm-svn: 348940
* [AMDGPU] Extend the SI Load/Store optimizer to combine more things.Neil Henning2018-12-124-238/+544
| | | | | | | | | | I've extended the load/store optimizer to be able to produce dwordx3 loads and stores, This change allows many more load/stores to be combined, and results in much more optimal code for our hardware. Differential Revision: https://reviews.llvm.org/D54042 llvm-svn: 348937
* [mips] Enable using of integrated assembler in all cases.Simon Atanasyan2018-12-121-21/+1
| | | | llvm-svn: 348934
* [TargetLowering] Add ISD::AND handling to SimplifyDemandedVectorEltsSimon Pilgrim2018-12-121-0/+16
| | | | | | | | If either of the operand elements are zero then we know the result element is going to be zero (even if the other element is undef). Differential Revision: https://reviews.llvm.org/D55558 llvm-svn: 348926
* [AMDGPU] Set metadata access for explicit sectionPiotr Sobczak2018-12-122-0/+12
| | | | | | | | | | | | | | | | | | | Summary: This patch provides a means to set Metadata section kind for a global variable, if its explicit section name is prefixed with ".AMDGPU.metadata." This could be useful to make the global variable go to an ELF section without any section flags set. Reviewers: dstuttard, tpr, kzhuravl, nhaehnle, t-tye Reviewed By: dstuttard, kzhuravl Subscribers: llvm-commits, arsenm, jvesely, wdng, yaxunl, t-tye Differential Revision: https://reviews.llvm.org/D55267 llvm-svn: 348922
* [ARM GlobalISel] Select load/store for Thumb2Diana Picus2018-12-122-6/+34
| | | | | | | | | | | | Unfortunately we can't use TableGen for this because it doesn't yet support predicates on the source pattern root. Therefore, add a bit of handwritten code to the instruction selector to handle the most basic cases. Also mark them as legal and extract their legalizer test cases to a new test file. llvm-svn: 348920
* [SystemZ] Minor cleanup of SchedModelsJonas Paulsson2018-12-122-21/+21
| | | | | | | Some fixes of a few InstRWs for z13 and z14. Review: Ulrich Weigand llvm-svn: 348917
* Fix compiler warning about unused variable [NFC]Mikael Holmen2018-12-121-1/+1
| | | | llvm-svn: 348913
* [Intrinsic] Signed Fixed Point Multiplication IntrinsicLeonard Chan2018-12-1210-5/+258
| | | | | | | | | | | | Add an intrinsic that takes 2 signed integers with the scale of them provided as the third argument and performs fixed point multiplication on them. This is a part of implementing fixed point arithmetic in clang where some of the more complex operations will be implemented as intrinsics. Differential Revision: https://reviews.llvm.org/D54719 llvm-svn: 348912
* [X86] Combine vpmovdw+vpacksswb into vpmovdb.Craig Topper2018-12-121-8/+8
| | | | | | This is similar to the combine we already have for vpmovdw+vpackuswb. llvm-svn: 348910
* [ConstantInt] Check active bits before calling getZExtValue.Florian Hahn2018-12-121-1/+5
| | | | | | | | | | | | | | | | | | Without this check, we hit an assertion in getZExtValue, if the constant value does not fit into an uint64_t. As getZExtValue returns an uint64_t, should we update getAggregateElement to take an uin64_t as well? This fixes https://bugs.chromium.org/p/oss-fuzz/issues/detail?id=6109. Reviewers: efriedma, craig.topper, spatel Reviewed By: efriedma Differential Revision: https://reviews.llvm.org/D55547 llvm-svn: 348906
* Implement IMAGE_REL_AMD64_SECREL for RuntimeDyldCOFFX86_64Nathan Lanza2018-12-121-0/+7
| | | | | | | | lldb on Windows uses the ExecutionEngine for expression evaluation and hits the llvm_unreachable due to this relocation. Thus, implement the relocation and add a test to verify it's function. llvm-svn: 348904
* [codeview] Look through typedefs in getCompleteTypeIndexReid Kleckner2018-12-111-0/+8
| | | | | | | | | | | | | | | | | Summary: Any time a symbol record, whether it's S_UDT, S_LOCAL, or S_[GL]DATA32, references a record type, it should use the complete type index, even if there's a typedef in the way. Fixes the compiler part of PR39853. Reviewers: zturner, aganea Subscribers: hiraditya, arphaman, llvm-commits Differential Revision: https://reviews.llvm.org/D55236 llvm-svn: 348902
* [GISel] Add parentheses to an assert because gcc is mean.Craig Topper2018-12-111-1/+1
| | | | llvm-svn: 348900
* Revert "debuginfo: Use symbol difference for CU length to simplify assembly ↵Jordan Rupprecht2018-12-113-16/+1
| | | | | | | | reading/editing" Temporarily reverts commit r348806 due to strange asm compilation issues in certain modes (combination of asan+cuda+other things). Will provide repro soon. llvm-svn: 348898
* [coroutines] Improve suspend point simplificationGor Nishanov2018-12-111-32/+100
| | | | | | | | | | | | | | | | | Summary: Enable suspend point simplification for cases where: * coro.save and coro.suspend are in different basic blocks * where there are intervening intrinsics Reviewers: modocache, tks2103, lewissbaker Reviewed By: modocache Subscribers: EricWF, llvm-commits Differential Revision: https://reviews.llvm.org/D55160 llvm-svn: 348897
* [Debuginfo] Prevent CodeGenPrepare from dropping debuginfo references.Wolfgang Pieb2018-12-111-0/+15
| | | | | | | | | | | | | | This fixes PR39845. CodeGenPrepare employs a transactional model when performing optimizations, i.e. it changes the IR to attempt an optimization and rolls back the change when it finds the change inadequate. It is during the rollback that references to locals were dropped from debug value intrinsics. This patch reinstates debuginfo references during rollbacks. Reviewers: aprantl, vsk Differential Revision: https://reviews.llvm.org/D55396 llvm-svn: 348896
* [ConstantFolding] Handle leading zero-size elements in load foldingNikita Popov2018-12-111-2/+13
| | | | | | | | | | | | | | | | | | | | | Struct types may have leading zero-size elements like [0 x i32], in which case the "real" element at offset 0 will not necessarily coincide with the 0th element of the aggregate. ConstantFoldLoadThroughBitcast() wants to drill down the element at offset 0, but currently always picks the 0th aggregate element to do so. This patch changes the code to find the first non-zero-size element instead, for the struct case. The motivation behind this change is https://github.com/rust-lang/rust/issues/48627. Rust is fond of emitting [0 x iN] separators between struct elements to enforce alignment, which prevents constant folding in this particular case. The additional tests with [4294967295 x [0 x i32]] check that we don't end up unnecessarily looping over a large number of zero-size elements of a zero-size array. Differential Revision: https://reviews.llvm.org/D55169 llvm-svn: 348895
* [GISel]: Add MachineIRBuilder support for passing in Flags while buildingAditya Nandakumar2018-12-111-1/+4
| | | | | | | | | | | | https://reviews.llvm.org/D55516 Add the ability to pass in flags to buildInstr calls. Currently no validation is performed but that can be easily performed based on the opcode (if necessary). Reviewed by: paquette. llvm-svn: 348893
* [NewPM] fixing asserts on deleted loop in -print-after-allFedor Sergeev2018-12-114-9/+17
| | | | | | | | | | | IR-printing AfterPass instrumentation might be called on a loop that has just been invalidated. We should skip printing it to avoid spurious asserts. Reviewed By: chandlerc, philip.pfaffe Differential Revision: https://reviews.llvm.org/D54740 llvm-svn: 348887
* [COFF, ARM64] Emit COFF function headerMandeep Singh Grang2018-12-111-5/+27
| | | | | | | | | | | | | | | | | | | | Summary: Emit COFF header when printing out the function. This is important as the header contains two important pieces of information: the storage class for the symbol and the symbol type information. This bit of information is required for the linker to correctly identify the type of symbol that it is dealing with. This patch mimics X86 and ARM COFF behavior for function header emission. Reviewers: rnk, mstorsjo, compnerd, TomTan, ssijaric Reviewed By: mstorsjo Subscribers: dmajor, javed.absar, kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D55535 llvm-svn: 348875
* [HotColdSplitting] Disable outlining landingpad instructions (PR39917)Vedant Kumar2018-12-111-1/+1
| | | | | | | | | | It's currently not safe to outline landingpad instructions (see llvm.org/PR39917). Like @llvm.eh.typeid.for, the order and content of previous landingpad instructions in a function alters the lowering of subsequent landingpads by renumbering type info ID's. Outlining a landingpad therefore breaks exception handling & unwinding. llvm-svn: 348870
* [InstCombine] try to convert x86 movmsk intrinsic to generic IR (PR39927)Sanjay Patel2018-12-111-20/+38
| | | | | | | | | | | | | call iM movmsk(sext <N x i1> X) --> zext (bitcast <N x i1> X to iN) to iM This has the potential to create less-than-8-bit scalar types as shown in some of the test diffs, but it looks like the backend knows how to deal with that in these patterns. This is the simple part of the fix suggested in: https://bugs.llvm.org/show_bug.cgi?id=39927 Differential Revision: https://reviews.llvm.org/D55529 llvm-svn: 348862
* Fix not correct imm operand assertion for SUB32ri in ↵Craig Topper2018-12-111-1/+2
| | | | | | | | | | | | | | | | | | | | | | | X86CondBrFolding::analyzeCompare Summary: When doing X86CondBrFolding::analyzeCompare, it will meet the SUB32ri instruction as below to use the global address for its operand, %733:gr32 = SUB32ri %62:gr32(tied-def 0), @img2buf_normal, implicit-def $eflags JNE_1 %bb.41, implicit $eflags so the assertion "assert(MI.getOperand(ValueIndex).isImm() && "Expecting Imm operand")" is not correct and change the assert to if make X86CondBrFolding::analyzeCompare return false as not finding the compare for this Patch by Jianping Chen Reviewers: smaslov, LuoYuanke, liutianle, Jianping Reviewed By: Jianping Subscribers: lebedev.ri, llvm-commits Differential Revision: https://reviews.llvm.org/D54250 llvm-svn: 348853
* [x86] clean up code for converting 16-bit ops to LEA; NFCSanjay Patel2018-12-112-62/+60
| | | | | | | | As discussed in D55494, we want to extend this to handle 8-bit ops too, but that could be extended further to enable this on 32-bit systems too. llvm-svn: 348851
* [x86] remove dead code for 16-bit LEA formation; NFCSanjay Patel2018-12-111-57/+13
| | | | | | | | | | | As discussed in: D55494 ...this code has been disabled/dead for a long time (the code references Athlon and Pentium 4), and there's almost no chance that it will be used given the last decade of uarch evolution. Also, in SDAG we promote 16-bit ops to 32-bit, so there's almost no way to test this code any more. llvm-svn: 348845
* Revert r348843 "[CodeGen] Allow mempcy/memset to generate small overlapping ↵Clement Courbet2018-12-111-3/+5
| | | | | | | | stores." Breaks ARM/memcpy-inline.ll llvm-svn: 348844
* [CodeGen] Allow mempcy/memset to generate small overlapping stores.Clement Courbet2018-12-111-5/+3
| | | | | | | | | | | | | Summary: All targets either just return false here or properly model `Fast`, so I don't think there is any reason to prevent CodeGen from doing the right thing here. Subscribers: nemanjai, javed.absar, eraman, jsji, llvm-commits Differential Revision: https://reviews.llvm.org/D55365 llvm-svn: 348843
* [TargetLowering] Add ISD::EXTRACT_VECTOR_ELT support to SimplifyDemandedBitsSimon Pilgrim2018-12-111-0/+19
| | | | | | | | Let SimplifyDemandedBits attempt to simplify all elements of a vector extraction. Part of PR39689. llvm-svn: 348839
* [DeadArgElim] Fixes for dbg.values using dead arg/return valuesDavid Stenberg2018-12-111-8/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: When eliminating a dead argument or return value in a function with local linkage, all uses, including in dbg.value intrinsics, would be replaced with null constants. This would mean that, for example for an integer argument, the debug info would incorrectly express that the value is 0. Instead, replace all uses with undef to indicate that the argument/return value is optimized out. Also, make sure that metadata uses of return values are rewritten even if there are no non-metadata uses of the value. As a bit of historical curiosity, the code that emitted null constants was introduced in the initial check-in of the pass in 2003, before 'undef' values even existed in LLVM. This fixes PR23260. Reviewers: dblaikie, aprantl, vsk, djtodoro Reviewed By: aprantl Subscribers: llvm-commits Tags: #debug-info Differential Revision: https://reviews.llvm.org/D55513 llvm-svn: 348837
* [PPC][NFC] store operands are dst not srcMartell Malone2018-12-111-9/+9
| | | | | | Differential Revision: https://reviews.llvm.org/D55502 llvm-svn: 348826
* [WebAssembly] Add '.eventtype' directive supportHeejin Ahn2018-12-113-33/+70
| | | | | | | | | | | | | | Summary: This patch supports `.eventtype` directive printing and parsing in the same syntax with `.functype`. Reviewers: aardappel, sbc100 Subscribers: dschuff, sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D55353 llvm-svn: 348818
* [TextAPI][elfabi] Make SoName optionalArmando Montanez2018-12-111-1/+1
| | | | | | | | | | | This change makes DT_SONAME treated as an optional trait for ELF TextAPI stubs. This change accounts for the fact that shared objects aren't guaranteed to have a DT_SONAME entry. Tests have been updated to check for correct behavior of an optional soname. Differential Revision: https://reviews.llvm.org/D55533 llvm-svn: 348817
* [WebAssembly] TargetStreamer cleanup (NFC)Heejin Ahn2018-12-113-42/+32
| | | | | | | | | | | | | | | | | | Summary: - Unify mixed argument names (`Symbol` and `Sym`) to `Sym` - Changed `MCSymbolWasm*` argument of `emit***` functions to `const MCSymbolWasm*`. It seems not very intuitive that emit function in the streamer modifies symbol contents. - Moved empty function bodies to the header - clang-format Reviewers: aardappel, dschuff, sbc100 Subscribers: jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D55347 llvm-svn: 348816
* [GISel]: Refactor MachineIRBuilder to allow passing additional parameters to ↵Aditya Nandakumar2018-12-115-405/+496
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | build Instrs https://reviews.llvm.org/D55294 Previously MachineIRBuilder::buildInstr used to accept variadic arguments for sources (which were either unsigned or MachineInstrBuilder). While this worked well in common cases, it doesn't allow us to build instructions that have multiple destinations. Additionally passing in other optional parameters in the end (such as flags) is not possible trivially. Also a trivial call such as B.buildInstr(Opc, Reg1, Reg2, Reg3) can be interpreted differently based on the opcode (2defs + 1 src for unmerge vs 1 def + 2srcs). This patch refactors the buildInstr to buildInstr(Opc, ArrayRef<DstOps>, ArrayRef<SrcOps>) where DstOps and SrcOps are typed unions that know how to add itself to MachineInstrBuilder. After this patch, most invocations would look like B.buildInstr(Opc, {s32, DstReg}, {SrcRegs..., SrcMIBs..}); Now all the other calls (such as buildAdd, buildSub etc) forward to buildInstr. It also makes it possible to build instructions with multiple defs. Additionally in a subsequent patch, we should make it possible to add flags directly while building instructions. Additionally, the main buildInstr method is now virtual and other builders now only have to override buildInstr (for say constant folding/cseing) is straightforward. Also attached here (https://reviews.llvm.org/F7675680) is a clang-tidy patch that should upgrade the API calls if necessary. llvm-svn: 348815
* debuginfo: Use symbol difference for CU length to simplify assembly ↵David Blaikie2018-12-103-1/+16
| | | | | | | | | | | | reading/editing Mucking about simplifying a test case ( https://reviews.llvm.org/D55261 ) I stumbled across something I've hit before - that LLVM's (GCC's does too, FWIW) assembly output includes a hardcode length for a DWARF unit in its header. Instead we could emit a label difference - making the assembly easier to read/edit (though potentially at a slight (I haven't tried to observe it) performance cost of delaying/sinking the length computation into the MC layer). Reviewers: JDevlieghere, probinson, ABataev Differential Revision: https://reviews.llvm.org/D55281 llvm-svn: 348806
* [Local] Promote an utility that could be used elsewhere. NFCI.Davide Italiano2018-12-102-7/+12
| | | | llvm-svn: 348804
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