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* [Hexagon] Couple of fixes in optimize addressing modeKrzysztof Parzyszek2018-12-101-16/+21
| | | | | | | | | | - Check if an operand is an immediate before calling getImm. Some operands that take constant values can actually have global symbols or other constant expressions. - When a load-constant instruction can be folded into users, make sure to only delete it when all users have been successfully converted. llvm-svn: 348802
* InstCombine: Scalarize single use icmp/fcmpMatt Arsenault2018-12-101-0/+12
| | | | llvm-svn: 348801
* Revert "[Hexagon] Check if operand is an immediate before getImm"Krzysztof Parzyszek2018-12-101-15/+12
| | | | | | This reverts r348787. The patch wasn't quite correct. llvm-svn: 348792
* APFloat: allow 64-bit of payloadJF Bastien2018-12-101-2/+24
| | | | | | | | | | | | | | | | | | | | Summary: The APFloat and Constant APIs taking an APInt allow arbitrary payloads, and that's great. There's a convenience API which takes an unsigned, and that's silly because it then directly creates a 64-bit APInt. Just change it to 64-bits directly. At the same time, add ConstantFP NaN getters which match the APFloat ones (with getQNaN / getSNaN and APInt parameters). Improve the APFloat testing to set more payload bits. Reviewers: scanon, rjmccall Subscribers: jkorous, dexonsmith, kristina, llvm-commits Differential Revision: https://reviews.llvm.org/D55460 llvm-svn: 348791
* [GlobalISel] Restrict G_MERGE_VALUES capability and replace with new opcodes.Amara Emerson2018-12-1010-22/+229
| | | | | | | | | | | | This patch restricts the capability of G_MERGE_VALUES, and uses the new G_BUILD_VECTOR and G_CONCAT_VECTORS opcodes instead in the appropriate places. This patch also includes AArch64 support for selecting G_BUILD_VECTOR of <4 x s32> and <2 x s64> vectors. Differential Revisions: https://reviews.llvm.org/D53629 llvm-svn: 348788
* [Hexagon] Check if operand is an immediate before getImmKrzysztof Parzyszek2018-12-101-12/+15
| | | | llvm-svn: 348787
* [Hexagon] Add patterns for any_extend from i1 and short vectors of i1Krzysztof Parzyszek2018-12-101-29/+28
| | | | llvm-svn: 348785
* [TargetLowering] Add UNDEF folding to SimplifyDemandedVectorEltsSimon Pilgrim2018-12-101-1/+6
| | | | | | | | | | If all the demanded elements of the SimplifyDemandedVectorElts are known to be UNDEF, we can simplify to an ISD::UNDEF node. Zero constant folding will be handled in a future patch - its a little trickier as we often have bitcasted zero values. Differential Revision: https://reviews.llvm.org/D55511 llvm-svn: 348784
* [DAGCombiner] Remove unnecessary recursive ↵Simon Pilgrim2018-12-101-6/+0
| | | | | | | | DAGCombiner::visitINSERT_SUBVECTOR call. As discussed on D55511, this caused an issue if the inner node deletes a node that the outer node depends upon. As it doesn't affect any lit-tests and I've only been able to expose this with the D55511 change I'm committing this now. llvm-svn: 348781
* [x86] fix formatting; NFCSanjay Patel2018-12-101-19/+17
| | | | | | | | This should really be generalized to allow increment and/or we should replace it by using ISD::matchUnaryPredicate(). See D55515 for context. llvm-svn: 348776
* [AArch64] Refactor the Exynos scheduling predicatesEvandro Menezes2018-12-106-329/+249
| | | | | | | | | Refactor the scheduling predicates based on `MCInstPredicate`. In this case, for the Exynos processors. Differential revision: https://reviews.llvm.org/D55345 llvm-svn: 348774
* [AMDGPU] Change the l1 flush instruction for AMDPAL/MESA3D.Neil Henning2018-12-101-1/+7
| | | | | | | | | | This commit changes which l1 flush instruction is used for AMDPAL and MESA3d workloads to flush the entire l1 cache instead of just the volatile lines. Differential Revision: https://reviews.llvm.org/D55367 llvm-svn: 348771
* [AArch64] Refactor the scheduling predicatesEvandro Menezes2018-12-101-61/+325
| | | | | | | | | Refactor the scheduling predicates based on `MCInstPredicate`. Augment the number of helper predicates used by processor specific predicates. Differential revision: https://reviews.llvm.org/D55375 llvm-svn: 348768
* [AMDGPU] Add new Mode Register pass - minor fixTim Corringham2018-12-101-1/+1
| | | | | | | Trivial change to add parentheses to an expression to avoid a sanitizer error in SIModeRegister.cpp, which was committed earlier. llvm-svn: 348767
* [AVX512] Update typo in commentCameron McInally2018-12-101-1/+1
| | | | | | | | Should be "Sae" for "Suppress All Exceptions". NFC llvm-svn: 348763
* [GlobalISel] Set stack protector index when translating ↵Petr Pavlu2018-12-101-5/+7
| | | | | | | | | | | | | | | | | | Intrinsic::stackprotector Record the stack protector index in MachineFrameInfo when translating Intrinsic::stackprotector similarly as is done by SelectionDAG when processing the same intrinsic. Setting this index allows the Prologue/Epilogue Insertion to recognize that the stack protection is enabled. The pass can then make sure that the stack protector comes before local variables on the stack and assigns potentially vulnerable objects first so they are close to the stack protector slot. Differential Revision: https://reviews.llvm.org/D55418 llvm-svn: 348761
* [mips][mc] Emit R_{MICRO}MIPS_JALR when expanding jal to jalrVladimir Stefanovic2018-12-101-3/+21
| | | | | | | | | | | When replacing jal with jalr, also emit '.reloc R_MIPS_JALR' (R_MICROMIPS_JALR for micromips). The linker might then be able to turn jalr into a direct call. Add '-mips-jalr-reloc' to enable/disable this feature (default is true). Differential revision: https://reviews.llvm.org/D55292 llvm-svn: 348760
* [DAGCombiner] Use the result value type in visitCONCAT_VECTORSFrancis Visoiu Mistrih2018-12-101-1/+1
| | | | | | | | | | | | | | | This triggers an assert when combining concat_vectors of a bitcast of merge_values. With asserts disabled, it fails to select: fatal error: error in backend: Cannot select: 0x7ff19d000e90: i32 = any_extend 0x7ff19d000ae8 0x7ff19d000ae8: f64,ch = CopyFromReg 0x7ff19d000c20:1, Register:f64 %1 0x7ff19d000b50: f64 = Register %1 In function: d Differential Revision: https://reviews.llvm.org/D55507 llvm-svn: 348759
* [AMDGPU] Add new Mode Register passTim Corringham2018-12-1011-11/+487
| | | | | | | | | | | | | | | A new pass to manage the Mode register. Currently this just manages the floating point double precision rounding requirements, but is intended to be easily extended to encompass all Mode register settings. The immediate motivation comes from the requirement to use the round-to-zero rounding mode for the 16 bit interpolation instructions, where the rounding mode setting is shared between 16 and 64 bit operations. llvm-svn: 348754
* [DebugInfo] Don't drop dbg.value's of nullptrJeremy Morse2018-12-102-1/+5
| | | | | | | | | | | | | | | | | | | Currently, dbg.value's of "nullptr" are dropped when entering a SelectionDAG -- apparently just because of an oversight when recognising Values that are constant (see PR39787). This patch adds ConstantPointerNull to the list of constants that can be turned into DBG_VALUEs. The matter of what bit-value a null pointer constant in LLVM has was raised in this mailing list thread: http://lists.llvm.org/pipermail/llvm-dev/2018-December/128234.html Where it transpires LLVM relies on (IR) null pointers being zero valued, thus I've baked this assumption into the patch. Differential Revision: https://reviews.llvm.org/D55227 llvm-svn: 348753
* [DebugInfo] Emit undef DBG_VALUEs when SDNodes are optimised outJeremy Morse2018-12-105-11/+40
| | | | | | | | | | | | | | | | | | | | | | | | | | | This is a fix for PR39896, where dbg.value's of SDNodes that have been optimised out do not lead to "DBG_VALUE undef" instructions being created. Such undef instructions are necessary to terminate earlier variable ranges, otherwise variable values leak past the point where they're valid. The "invalidated" flag of SDDbgValue is currently being abused to mean two things: * The corresponding SDNode is now invalid * This SDDbgValue should not be emitted Of which there are several legitimate combinations of meaning: * The SDNode has been invalidated and we should emit "DBG_VALUE undef" * The SDNode has been invalidated but the debug data was salvaged, don't emit anything for this SDDbgValue * This SDDbgValue has been emitted This patch introduces distinct "Emitted" and "Invalidated" fields to the SDDbgValue class, updates users accordingly, and generates "undef" DBG_VALUEs for invalidated records. Awkwardly, there are circumstances where we emit SDDbgValue's twice, specifically DebugInfo/X86/dbg-addr-dse.ll which I've preserved. Differential Revision: https://reviews.llvm.org/D55372 llvm-svn: 348751
* [X86] Fix AvoidStoreForwardingBlocks pass for negative displacementsNikita Popov2018-12-101-1/+1
| | | | | | | | | | | | | | | | Fixes https://bugs.llvm.org/show_bug.cgi?id=39926. The size of the first copy was computed as std::abs(std::abs(LdDisp2) - std::abs(LdDisp1)), which results in skipped bytes if the signs of LdDisp2 and LdDisp1 differ. As far as I can see, this should just be LdDisp2 - LdDisp1. The case where LdDisp1 > LdDisp2 is already handled in the code above, in which case LdDisp2 is set to LdDisp1 and this subtraction will evaluate to Size1 = 0, which is the correct value to skip an overlapping copy. Differential Revision: https://reviews.llvm.org/D55485 llvm-svn: 348750
* [X86] Merge addcarryx/addcarry intrinsic into a single addcarry intrinsic.Craig Topper2018-12-102-65/+44
| | | | | | | | Both intrinsics do the exact same thing so we really only need one. Earlier in the 8.0 cycle we changed the signature of this intrinsic without renaming it. But it looks difficult to get the autoupgrade code to allow me to merge the intrinsics and change the signature at the same time. So I've renamed the intrinsic slightly for the new merged intrinsic. I'm skipping autoupgrading from the previous new to 8.0 signature. I've also renamed the subborrow for consistency. llvm-svn: 348737
* [TextAPI][elfabi] Fix build by adding std::move() to r348735Armando Montanez2018-12-101-1/+1
| | | | llvm-svn: 348736
* [TextAPI][elfabi] Make TBE handlers functions that return ErrorsArmando Montanez2018-12-101-4/+5
| | | | | | | | | | | | Since TBEHandler doesn't maintain state or otherwise have any need to be a class right now, the read and write functions have been moved out and turned into standalone functions. Additionally, the TBE read function has been updated to return an Expected value for better error handling. Tests have been updated to reflect these changes. Differential Revision: https://reviews.llvm.org/D55450 llvm-svn: 348735
* [AMDGPU] Fix discarded result of addAttributeBrian Gesiak2018-12-091-2/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: `llvm::AttributeList` and `llvm::AttributeSet` are immutable, and so methods defined on these classes, such as `addAttribute`, return a new immutable object with the attribute added. In https://reviews.llvm.org/D55217 I attempted to annotate methods such as `addAttribute` with `LLVM_NODISCARD`, since calling these methods has no side-effects, and so ignoring the result that is returned is almost certainly a programmer error. However, committing the change resulted in new warnings in the AMDGPU target. The AMDGPU simplify libcalls pass added in https://reviews.llvm.org/D36436 attempts to add the readonly and nounwind attributes to simplified library functions, but instead calls the `addAttribute` methods and ignores the result. Modify the simplify libcalls pass to actually add the nounwind and readonly attributes. Also update the simplify libcalls test to assert that these attributes are actually being set. Reviewers: rampitec, vpykhtin, rnk Reviewed By: rampitec Subscribers: arsenm, kzhuravl, jvesely, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye, llvm-commits Differential Revision: https://reviews.llvm.org/D55435 llvm-svn: 348732
* [X86] Add some comments about when some X86 intrinsic autoupgrade code was ↵Craig Topper2018-12-091-7/+7
| | | | | | | | added. Someday we'd like to remove old autoupgrade code so it helps to annotate how long its been there so we don't have to go digging through commit history. llvm-svn: 348728
* [X86] If the carry input to an addcarry/subborrow intrinsic is known to be ↵Craig Topper2018-12-092-10/+19
| | | | | | | | | | 0, emit a flag setting ADD/SUB instead of ADC/SBB. Previously we had to take the carry in and add -1 to it to set the carry flag so we could use it with ADC/SBB. But if we know its 0 then we don't need to bother. This should go a long way towards fixing PR24545. llvm-svn: 348727
* Remove unneeded dependency from lib/Target/X86/Utils/ to lib/IR (aka Core).Nico Weber2018-12-091-1/+1
| | | | | | | The dependency was added in r213995 in response to r213986 which did make X86/Utils depend on IR, but r256680 later removed that dependency again. llvm-svn: 348724
* [x86] don't try to convert add with undef operands to LEASanjay Patel2018-12-092-37/+36
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The existing code tries to handle an undef operand while transforming an add to an LEA, but it's incomplete because we will crash on the i16 test with the debug output shown below. It's better to just give up instead. Really, GlobalIsel should have folded these before we could get into trouble. # Machine code for function add_undef_i16: NoPHIs, TracksLiveness, Legalized, RegBankSelected, Selected bb.0 (%ir-block.0): liveins: $edi %1:gr32 = COPY killed $edi %0:gr16 = COPY %1.sub_16bit:gr32 %5:gr64_nosp = IMPLICIT_DEF %5.sub_16bit:gr64_nosp = COPY %0:gr16 %6:gr64_nosp = IMPLICIT_DEF %6.sub_16bit:gr64_nosp = COPY %2:gr16 %4:gr32 = LEA64_32r killed %5:gr64_nosp, 1, killed %6:gr64_nosp, 0, $noreg %3:gr16 = COPY killed %4.sub_16bit:gr32 $ax = COPY killed %3:gr16 RET 0, implicit killed $ax # End machine code for function add_undef_i16. *** Bad machine code: Reading virtual register without a def *** - function: add_undef_i16 - basic block: %bb.0 (0x7fe6cd83d940) - instruction: %6.sub_16bit:gr64_nosp = COPY %2:gr16 - operand 1: %2:gr16 LLVM ERROR: Found 1 machine code errors. Differential Revision: https://reviews.llvm.org/D54710 llvm-svn: 348722
* [X86] Extend pfm counter coverage for llvm-exegesisSimon Pilgrim2018-12-091-5/+29
| | | | | | Extension to rL348617, turns out llvm-exegesis doesn't need to match the perf counter name against a scheduler model resource name - so I've added a few more counters that I could find in the libpfm4 source code (and fix a typo in the knl/knm retired_uops counter - which uses 'all' instead of 'any'). llvm-svn: 348721
* [COFF] Map truncated .eh_frame section nameMartin Storsjo2018-12-081-0/+6
| | | | | | | | | | | | | | | PE/COFF sections can have section names truncated to 8 chars, in order to have the name available at runtime. (The string table, where long untruncated names are stored, isn't loaded at runtime.) This allows various llvm tools to dump the .eh_frame section from such executables. Patch by Peiyuan Song! Differential Revision: https://reviews.llvm.org/D55407 llvm-svn: 348708
* [DAGCombiner] re-enable truncation of binopsSanjay Patel2018-12-081-12/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is effectively re-committing the changes from: rL347917 (D54640) rL348195 (D55126) ...which were effectively reverted here: rL348604 ...because the code had a bug that could induce infinite looping or eventual out-of-memory compilation. The bug was that this code did not guard against transforming opaque constants. More details are in the post-commit mailing list thread for r347917. A reduced test for that is included in the x86 bool-math.ll file. (I wasn't able to reduce a PPC backend test for this, but it was almost the same pattern.) Original commit message for r347917: The motivating case for this is shown in: https://bugs.llvm.org/show_bug.cgi?id=32023 and the corresponding rot16.ll regression tests. Because x86 scalar shift amounts are i8 values, we can end up with trunc-binop-trunc sequences that don't get folded in IR. As the TODO comments suggest, there will be regressions if we extend this (for x86, we mostly seem to be missing LEA opportunities, but there are likely vector folds missing too). I think those should be considered existing bugs because this is the same transform that we do as an IR canonicalization in instcombine. We just need more tests to make those visible independent of this patch. llvm-svn: 348706
* [WebAssembly] Make WasmSymbol's signature usable for events (NFC)Heejin Ahn2018-12-081-5/+7
| | | | | | | | | | | | | | Summary: WasmSignature used to use its `WasmSignature` member variable only for function types, but now it also can be used for events as well. Reviewers: sbc100 Subscribers: dschuff, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D55247 llvm-svn: 348702
* [SelectionDAG] Remove ISD::ADDC/ADDE from some undef handling code in ↵Craig Topper2018-12-081-2/+0
| | | | | | | | getNode. NFCI These nodes should have two results. A real VT and a Glue. But this code would have returned Undef which would only be a single result. But we're in the single result version of getNode so these opcodes should never be seen by this function anyway. llvm-svn: 348670
* AMDGPU: Fix offsets for < 4-byte aggregate kernel argumentsMatt Arsenault2018-12-071-4/+7
| | | | | | | | We were still using the rounded down offset and alignment even though they aren't handled because you can't trivially bitcast the loaded value. llvm-svn: 348658
* [GlobalISel] Add IR translation support for the @llvm.log10 intrinsicJessica Paquette2018-12-071-0/+5
| | | | | | | | This adds IR translation support for @llvm.log10 and updates relevant tests. https://reviews.llvm.org/D55392 llvm-svn: 348657
* [Hexagon] Fix post-ra expansion of PS_wselectKrzysztof Parzyszek2018-12-071-1/+0
| | | | llvm-svn: 348655
* [ModuleSummary] use StringRefs to avoid a redundant copy; NFCGeorge Burgess IV2018-12-071-1/+1
| | | | | | | | `Saver` is a StringSaver, which has a few overloads of `save` that all ultimately just call `StringRef save(StringRef)`. Just take a StringRef here instead of building up a std::string to convert it to a StringRef. llvm-svn: 348650
* Fix unused variable warning. NFCI.Simon Pilgrim2018-12-071-2/+2
| | | | llvm-svn: 348649
* [WebAssembly] clang-format/clang-tidy AsmParser (NFC)Heejin Ahn2018-12-071-60/+88
| | | | | | | | | | | | | | | | | | | Summary: - LLVM clang-format style doesn't allow one-line ifs. - LLVM clang-tidy style says method names should start with a lowercase letter. But currently WebAssemblyAsmParser's parent class MCTargetAsmParser is mixing lowercase and uppercase method names itself so overridden methods cannot be renamed now. - Changed else ifs after returns to ifs. - Added some newlines for readability. Reviewers: aardappel, sbc100 Subscribers: dschuff, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D55350 llvm-svn: 348648
* Delete registerScope functionHeejin Ahn2018-12-071-20/+2
| | | | | | `unregisterScope()` is not currently used, so removing it. llvm-svn: 348647
* Follow-up from r348441 to add the rest of the objc ARC intrinsics.Pete Cooper2018-12-071-0/+14
| | | | | | This adds the other intrinsics used by ARC and codegen's them to their respective runtime methods. llvm-svn: 348646
* [MemCpyOpt] memset->memcpy forwarding with undef tailNikita Popov2018-12-072-16/+36
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently memcpyopt optimizes cases like memset(a, byte, N); memcpy(b, a, M); to memset(a, byte, N); memset(b, byte, M); if M <= N. Often this allows further simplifications down the line, which drop the first memset entirely. This patch extends this optimization for the case where M > N, but we know that the bytes a[N..M] are undef due to alloca/lifetime.start. This situation arises relatively often for Rust code, because Rust does not initialize trailing structure padding and loves to insert redundant memcpys. This also fixes https://bugs.llvm.org/show_bug.cgi?id=39844. For the implementation, I'm reusing a bit of code for a similar existing optimization (direct memcpy of undef). I've also added memset support to MemDepAnalysis GetLocation -- Instead, getPointerDependencyFrom could be used, but it seems to make more sense to add this to GetLocation and thus make the computation cachable. Differential Revision: https://reviews.llvm.org/D55120 llvm-svn: 348645
* [HotColdSplitting] Refine definition of unlikelyExecutedVedant Kumar2018-12-071-24/+16
| | | | | | | | | | | | | | | | | | | | | | | The splitting pass uses its 'unlikelyExecuted' predicate to statically decide which blocks are cold. - Do not treat noreturn calls as if they are cold unless they are actually marked cold. This is motivated by functions like exit() and longjmp(), which are not beneficial to outline. - Do not treat inline asm as an outlining barrier. In practice asm("") is frequently used to inhibit basic block merging; enabling outlining in this case results in substantial memory savings. - Treat invokes of cold functions as cold. As a drive-by, remove the 'exceptionHandlingFunctions' predicate, because it's no longer needed. The pass can identify & outline blocks dominated by EH pads, so there's no need to special-case __cxa_begin_catch etc. Differential Revision: https://reviews.llvm.org/D54244 llvm-svn: 348640
* [HotColdSplitting] Outline more than once per functionVedant Kumar2018-12-071-165/+287
| | | | | | | | | | | | | | | | | | Algorithm: Identify maximal cold regions and put them in a worklist. If a candidate region overlaps with another, discard it. While the worklist is full, remove a single-entry sub-region from the worklist and attempt to outline it. By the non-overlap property, this should not invalidate parts of the domtree pertaining to other outlining regions. Testing: LNT results on X86 are clean. With test-suite + externals, llvm outlines 134KB pre-patch, and 352KB post-patch (+ ~2.6x). The file 483.xalancbmk/src/Constants.cpp stands out as an extreme case where llvm outlines over 100 times in some functions (mostly EH paths). There was not a significant performance impact pre vs. post-patch. Differential Revision: https://reviews.llvm.org/D53887 llvm-svn: 348639
* [NativePDB] Reconstruct function declarations from debug info.Zachary Turner2018-12-071-1/+12
| | | | | | | | | | | | Previously we would create an lldb::Function object for each function parsed, but we would not add these to the clang AST. This is a first step towards getting local variable support working, as we first need an AST decl so that when we create local variable entries, they have the proper DeclContext. Differential Revision: https://reviews.llvm.org/D55384 llvm-svn: 348631
* [llvm-tapi] Don't try to override SequenceTraits for std::stringSam Clegg2018-12-071-17/+0
| | | | | | | | | | | | | | | | For some reason this doesn't seem to work with LLVM_LINK_LLVM_DYLIB build. See https://logs.chromium.org/logs/chromium/bb/client.wasm.llvm/linux/37764/+/recipes/steps/LLVM_regression_tests/0/stdout What is more it seems that overriding these traits for core types (including std::string) is not supported/recommend by YAMLTraits.h. See line 1918 which has the assertion: "only use LLVM_YAML_IS_SEQUENCE_VECTOR for types you control" Differential Revision: https://reviews.llvm.org/D55381 llvm-svn: 348630
* [DAGCombiner] split trunc from extend in hoistLogicOpWithSameOpcodeHands; NFCSanjay Patel2018-12-071-33/+48
| | | | | | | This duplicates several shared checks, but we need to split this up to fix underlying bugs in smaller steps. llvm-svn: 348627
* [X86] Replace instregex with instrs list. NFCI. Simon Pilgrim2018-12-073-3/+3
| | | | llvm-svn: 348626
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