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* [MachineLICM] First steps of sinking GEPs near calls.Daniel Jasper2015-03-141-0/+61
| | | | | | | | | | | | | | | Specifically, if there are copy-like instructions in the loop header they are moved into the loop close to their uses. This reduces the live intervals of the values and can avoid register spills. This is working towards a fix for http://llvm.org/PR22230. Review: http://reviews.llvm.org/D7259 Next steps: - Find a better cost model (which non-copy instructions should be sunk?) - Make this dependent on register pressure llvm-svn: 232262
* [mips] Remove trivial header for the MipsModuleISelDAGToDAG pass. NFC.Vasileios Kalintiris2015-03-144-60/+20
| | | | llvm-svn: 232260
* [mips] Remove trivial header for the Mips16HardFloat pass. NFC.Vasileios Kalintiris2015-03-144-129/+97
| | | | llvm-svn: 232259
* [mips] Remove trivial header for the MipsOs16 pass. NFC.Vasileios Kalintiris2015-03-144-93/+72
| | | | llvm-svn: 232258
* [opaque pointer type] Start migrating GEP creation to explicitly specify the ↵David Blaikie2015-03-145-32/+35
| | | | | | | | | | | | | | | pointee type I'm just going to migrate these in a pretty ad-hoc & incremental way - providing the backwards compatible API for now, then locally removing it, fixing a few callers, adding it back in and commiting those callers. Rinse, repeat. The assertions should ensure that if I get this wrong we'll find out about it and not just have one giant patch to revert, recommit, revert, recommit, etc. llvm-svn: 232240
* CommandLine: Replace cold std::sort with array_pod_sort.Benjamin Kramer2015-03-141-11/+12
| | | | | | | | | Also replace an old use of qsort with it. Compiles down to the same thing but gives us some type safety. Safes a couple of kb on CommandLine.o. NFC. llvm-svn: 232236
* LowerBitSets: Do not export symbols for bit set referenced globals on Darwin.Peter Collingbourne2015-03-141-1/+9
| | | | | | | The linker on that platform may re-order symbols or strip dead symbols, which will break bit set checks. Avoid this by hiding the symbols from the linker. llvm-svn: 232235
* Use add32ri8 and friends on fast isel.Rafael Espindola2015-03-131-5/+5
| | | | | | | | | | | | | | | This fixes pr22854. The core issue on the bug is that there are multiple instructions that print the same in assembly. In fact, there doesn't seem to be any syntax for specifying that a constant that fits in 8 bits should use a 32 bit immediate. The attached patch changes fast isel to consider i16immSExt8, i32immSExt8, and i64immSExt8. They were disabled because fastisel didn’t know to call the predicate back in the day. llvm-svn: 232223
* bpf: turn on HasJIT flag in BPF backendAlexei Starovoitov2015-03-131-1/+1
| | | | | | basic tests that use BPF backend to produce code in memory are passing. llvm-svn: 232222
* Be lazy about loading metadata in IRObjectFile.Rafael Espindola2015-03-133-2/+10
| | | | | | | This speeds up llvm-ar building lib64/libclangSema.a with debug IR files from 8.658015807 seconds to just 0.351036519 seconds :-) llvm-svn: 232221
* BranchFolding: MergePotentialsElt has a total order, just call array_pod_sort.Benjamin Kramer2015-03-131-1/+1
| | | | | | No functionality change intended. llvm-svn: 232217
* [opaque pointer type] Bitcode support for explicit type parameter on the gep ↵David Blaikie2015-03-132-7/+16
| | | | | | | | | | | | | | operator This happened to be fairly easy to support backwards compatibility based on the number of operands (old format had an even number, new format has one more operand so an odd number). test/Bitcode/old-aliases.ll already appears to test old gep operators (if I remove the backwards compatibility in the BitcodeReader, this and another test fail) so I'm not adding extra test coverage here. llvm-svn: 232216
* Turn assertion into bitcode reading errorDavid Blaikie2015-03-131-2/+2
| | | | | | | | I don't think we test invalid bitcode records in any detail, so no test here - just a change for consistency with existing error checks in surrounding code. llvm-svn: 232215
* Reapply "[Reassociate] Add initial support for vector instructions."Robert Lougher2015-03-131-19/+15
| | | | | | | | | This reapplies the patch previously committed at revision 232190. This was reverted at revision 232196 as it caused test failures in tests that did not expect operands to be commuted. I have made the tests more resilient to reassociation in revision 232206. llvm-svn: 232209
* bpf: fix buildAlexei Starovoitov2015-03-133-3/+0
| | | | | | | fix missed bits which were left over after r231987 Signed-off-by: Alexei Starovoitov <ast@plumgrid.com> llvm-svn: 232208
* instcombine: alloca: Canonicalize scalar allocation array sizeDuncan P. N. Exon Smith2015-03-131-2/+10
| | | | | | | | | As a follow-up to r232200, add an `-instcombine` to canonicalize scalar allocations to `i32 1`. Since r232200, `iX 1` (for X != 32) are only created by RAUWs, so this shouldn't fire too often. Nevertheless, it's a cheap check and a nice cleanup. llvm-svn: 232202
* instcombine: alloca: Limit array size type promotionDuncan P. N. Exon Smith2015-03-131-9/+9
| | | | | | | | | | | | | | Move type promotion of the size of the array allocation to the end of `simplifyAllocaArraySize()`. This avoids promoting the type of the array size if it's a `ConstantInt`, since the next -instcombine iteration will drop it to a scalar allocation anyway. Similarly, this avoids promoting the type if it's an `UndefValue`, in which case the alloca gets RAUW'ed. This is NFC when considered over the lifetime of -instcombine, since it's just reducing the number of iterations needed to reach fixed point. llvm-svn: 232201
* AsmWriter: Write alloca array size explicitly (and -instcombine fixup)Duncan P. N. Exon Smith2015-03-132-5/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Write the `alloca` array size explicitly when it's non-canonical. Previously, if the array size was `iX 1` (where X is not 32), the type would mutate to `i32` when round-tripping through assembly. The testcase I added fails in `verify-uselistorder` (as well as `FileCheck`), since the use-lists for `i32 1` and `i64 1` change. (Manman Ren came across this when running `verify-uselistorder` on some non-trivial, optimized code as part of PR5680.) The type mutation started with r104911, which allowed array sizes to be something other than an `i32`. Starting with r204945, we "canonicalized" to `i64` on 64-bit platforms -- and then on every round-trip through assembly, mutated back to `i32`. I bundled a fixup for `-instcombine` to avoid r204945 on scalar allocations. (There wasn't a clean way to sequence this into two commits, since the assembly change on its own caused testcase churn, and the `-instcombine` change can't be tested without the assembly changes.) An obvious alternative fix -- change `AllocaInst::AllocaInst()`, `AsmWriter` and `LLParser` to treat `intptr_t` as the canonical type for scalar allocations -- was rejected out of hand, since this required teaching them each about the data layout. A follow-up commit will add an `-instcombine` to canonicalize the scalar allocation array size to `i32 1` rather than leaving `iX 1` alone. rdar://problem/20075773 llvm-svn: 232200
* instcombine: alloca: Remove nesting in simplifyAllocaArraySize(), NFCDuncan P. N. Exon Smith2015-03-131-27/+30
| | | | llvm-svn: 232199
* Add a parameter for getLazyBitcodeModule to lazily load Metadata.Manman Ren2015-03-133-12/+70
| | | | | | | | | | | | | | | | | | | | | | | | | | | We only defer loading metadata inside ParseModule when ShouldLazyLoadMetadata is true and we have not loaded any Metadata block yet. This commit implements all-or-nothing loading of Metadata. If there is a request to load any metadata block, we will load all deferred metadata blocks. We make sure the deferred metadata blocks are loaded before we materialize any function or a module. The default value of the added parameter ShouldLazyLoadMetadata for getLazyBitcodeModule is false, so the default behavior stays the same. We only set the parameter to true when creating LTOModule in local contexts. These can only really be used for parsing symbols, so it's unnecessary to ever load the metadata blocks. If we are going to enable lazy-loading of Metadata for other usages of getLazyBitcodeModule, where deferred metadata blocks need to be loaded, we can expose BitcodeReader::materializeMetadata to Module, similar to Module::materialize. rdar://19804575 llvm-svn: 232198
* instcombine: alloca: Split out simplifyAllocaArraySize(), NFCDuncan P. N. Exon Smith2015-03-131-8/+15
| | | | | | | | Follow-up commits will change some of the logic here. Splitting into a separate function simplifies the logic by allowing early returns instead of deeper nesting. llvm-svn: 232197
* Revert: "[Reassociate] Add initial support for vector instructions."Robert Lougher2015-03-131-15/+19
| | | | | | | This reverts revision 232190 due to buildbot failure reported on clang-hexagon-elf for test arm64_vtst.c. To be investigated. llvm-svn: 232196
* [Reassociate] Add initial support for vector instructions.Robert Lougher2015-03-131-19/+15
| | | | | | | | | | | | | | This patch adds initial support for vector instructions to the reassociation pass. It enables most parts of the pass to work with vectors but to keep the size of the patch small, optimization of Xor trees, canonicalization of negative constants and converting shifts to muls, etc., have been left out. This will be handled in later patches. The patch is based on an initial patch by Chad Rosier. Differential Revision: http://reviews.llvm.org/D7566 llvm-svn: 232190
* [SCEV] Fix PR22856.Sanjoy Das2015-03-131-3/+6
| | | | | | | | | | | | | | | | | | | | Summary: ScalarEvolutionExpander assumes that the header block of a loop is a legal place to have a use for a phi node. This is true only for phis that are either in the header or dominate the header block, but it is not true for phi nodes that are strictly internal to the loop body. This change teaches ScalarEvolutionExpander to place uses of PHI nodes in the basic block the PHI nodes belong to. This is always legal, and `hoistIVInc` ensures that the said position dominates `IsomorphicInc`. Reviewers: atrick Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D8311 llvm-svn: 232189
* [opaque pointer type] Add textual IR support for explicit type parameter to ↵David Blaikie2015-03-132-2/+26
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | gep operator Similar to gep (r230786) and load (r230794) changes. Similar migration script can be used to update test cases, which successfully migrated all of LLVM and Polly, but about 4 test cases needed manually changes in Clang. (this script will read the contents of stdin and massage it into stdout - wrap it in the 'apply.sh' script shown in previous commits + xargs to apply it over a large set of test cases) import fileinput import sys import re rep = re.compile(r"(getelementptr(?:\s+inbounds)?\s*\()((<\d*\s+x\s+)?([^@]*?)(|\s*addrspace\(\d+\))\s*\*(?(3)>)\s*)(?=$|%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|zeroinitializer|<|\[\[[a-zA-Z]|\{\{)", re.MULTILINE | re.DOTALL) def conv(match): line = match.group(1) line += match.group(4) line += ", " line += match.group(2) return line line = sys.stdin.read() off = 0 for match in re.finditer(rep, line): sys.stdout.write(line[off:match.start()]) sys.stdout.write(conv(match)) off = match.end() sys.stdout.write(line[off:]) llvm-svn: 232184
* r600: Clear visited structure before running.Jan Vesely2015-03-131-0/+1
| | | | | | | | Fixes random crashes in for-loop piglit. Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu> Reviewed-by: Matt Arsenault <Matthew.Arsenault@amd.com> llvm-svn: 232181
* r600: Use deque and simplify loops in AMDGPUCFGStructurizerJan Vesely2015-03-131-10/+10
| | | | | | Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu> Reviewed-by: Matt Arsenault <Matthew.Arsenault@amd.com> llvm-svn: 232180
* [X86][AVX] Fix wrong lowering of v4x64 shuffles into concat_vector plus ↵Andrea Di Biagio2015-03-131-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | extract_subvector nodes. This patch fixes a bug in the shuffle lowering logic implemented by function 'lowerV2X128VectorShuffle'. The are few cases where function 'lowerV2X128VectorShuffle' wrongly expands a shuffle of two v4X64 vectors into a CONCAT_VECTORS of two EXTRACT_SUBVECTOR nodes. The problematic expansion only occurs when the shuffle mask M has an 'undef' element at position 2, and M is equivalent to mask <0,1,4,5>. In that case, the algorithm propagates the wrong vector to one of the two new EXTRACT_SUBVECTOR nodes. Example: ;; define <4 x double> @test(<4 x double> %A, <4 x double> %B) { entry: %0 = shufflevector <4 x double> %A, <4 x double> %B, <4 x i32><i32 undef, i32 1, i32 undef, i32 5> ret <4 x double> %0 } ;; Before this patch, llc (-mattr=+avx) generated: vinsertf128 $1, %xmm0, %ymm0, %ymm0 With this patch, llc correctly generates: vinsertf128 $1, %xmm1, %ymm0, %ymm0 Added test lower-vec-shuffle-bug.ll Differential Revision: http://reviews.llvm.org/D8259 llvm-svn: 232179
* unique_ptrs are unique already, no need to unique them any further.Benjamin Kramer2015-03-131-8/+7
| | | | llvm-svn: 232178
* ConstantFold: Fix big shift constant foldingDavid Majnemer2015-03-131-21/+12
| | | | | | | | | | | | | Constant folding for shift IR instructions ignores all bits above 32 of second argument (shift amount). Because of that, some undef results are not recognized and APInt can raise an assert failure if second argument has more than 64 bits. Patch by Paweł Bylica! Differential Revision: http://reviews.llvm.org/D7701 llvm-svn: 232176
* Recommit r232027 with PR22883 fixed: Add infrastructure for support of ↵Daniel Sanders2015-03-1319-45/+82
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | multiple memory constraints. The operand flag word for ISD::INLINEASM nodes now contains a 15-bit memory constraint ID when the operand kind is Kind_Mem. This constraint ID is a numeric equivalent to the constraint code string and is converted with a target specific hook in TargetLowering. This patch maps all memory constraints to InlineAsm::Constraint_m so there is no functional change at this point. It just proves that using these previously unused bits in the encoding of the flag word doesn't break anything. The next patch will make each target preserve the current mapping of everything to Constraint_m for itself while changing the target independent implementation of the hook to return Constraint_Unknown appropriately. Each target will then be adapted in separate patches to use appropriate Constraint_* values. PR22883 was caused the matching operands copying the whole of the operand flags for the matched operand. This included the constraint id which needed to be replaced with the operand number. This has been fixed with a conversion function. Following on from this, matching operands also used the operand number as the constraint id. This has been fixed by looking up the matched operand and taking it from there. llvm-svn: 232165
* [mips] [IAS] Refactor MipsTargetStreamer::emitMipsAbiFlags(). NFC.Toma Tabacu2015-03-132-7/+1
| | | | | | | | | | | | | | Summary: Make emitMipsAbiFlags a direct member of MipsTargetELFStreamer, as that's the only place where it's used, and remove the empty implementations from MipsTargetStreamer and MipsTargetAsmStreamer. Reviewers: dsanders, rafael Reviewed By: rafael Subscribers: rafael, llvm-commits Differential Revision: http://reviews.llvm.org/D8199 llvm-svn: 232161
* Teach TBAA analysis to report errors on cyclic TBAA metadata rather than ↵Owen Anderson2015-03-131-4/+9
| | | | | | hanging. llvm-svn: 232144
* Fix an infinite recursion in the verifier caused by calling isSized on a ↵Owen Anderson2015-03-131-1/+2
| | | | | | recursive type. llvm-svn: 232143
* [MachineCopyPropagation] Fix a bug causing incorrect removal for the ↵Hao Liu2015-03-131-4/+3
| | | | | | | | | | | | | | instruction sequences as follows %Q5_Q6<def> = COPY %Q2_Q3 %D5<def> = %D3<def> = %D3<def> = COPY %D6 // Incorrectly removed in MachineCopyPropagation Using of %D3 results in incorrect result ... Reviewed in http://reviews.llvm.org/D8242 llvm-svn: 232142
* When forming an addrec out of a phi don't just look at the last computation ↵Nick Lewycky2015-03-131-5/+7
| | | | | | | | and steal its flags for our own, there may be other computations in the middle. Check whether the LHS of the computation is the phi itself and then we know it's safe to steal the flags. Fixes PR22795. There's a missed optimization opportunity where we could look at the full chain of computation and take the intersection of the flags instead of only looking one instruction deep. llvm-svn: 232134
* Use the cached subtarget off of the machine function.Eric Christopher2015-03-131-1/+1
| | | | llvm-svn: 232129
* Use the cached subtarget off of the machine function.Eric Christopher2015-03-131-6/+6
| | | | llvm-svn: 232128
* [X86, AVX2] Replace inserti128 and extracti128 intrinsics with generic shufflesSanjay Patel2015-03-123-27/+7
| | | | | | | | | | | | | | | | | This should complete the job started in r231794 and continued in r232045: We want to replace as much custom x86 shuffling via intrinsics as possible because pushing the code down the generic shuffle optimization path allows for better codegen and less complexity in LLVM. AVX2 introduced proper integer variants of the hacked integer insert/extract C intrinsics that were created for this same functionality with AVX1. This should complete the removal of insert/extract128 intrinsics. The Clang precursor patch for this change was checked in at r232109. llvm-svn: 232120
* Move a variable into the assert where it's used - fixes a -AssertsEric Christopher2015-03-121-2/+1
| | | | | | build warning/error. llvm-svn: 232119
* In preparation for moving ARM's TargetRegisterInfo to the TargetMachineEric Christopher2015-03-1212-146/+105
| | | | | | | merge Thumb1RegisterInfo and Thumb2RegisterInfo. This will enable us to match the TargetMachine for our TargetRegisterInfo classes. llvm-svn: 232117
* R600/SI: Don't print scc reg in sopc assembly stringTom Stellard2015-03-121-1/+1
| | | | | | This is how the proprietary driver prints sopc instructions. llvm-svn: 232106
* R600/SI: Remove _e32 and _e64 suffixes from mnemonicsTom Stellard2015-03-125-25/+41
| | | | | | | | Instead print them as part of the $dst operand. The AsmMatcher requires the 32-bit and 64-bit encodings have the same mnemonic in order to parse them correctly. llvm-svn: 232105
* Migrate the AArch64 TargetRegisterInfo to its TargetMachineEric Christopher2015-03-128-48/+52
| | | | | | | implementation. This requires a bit of scaffolding and a few fixups that'll go away once all of the ports have been migrated. llvm-svn: 232103
* Remove unused headers.Eric Christopher2015-03-121-2/+0
| | | | llvm-svn: 232102
* Revert "r232027 - Add infrastructure for support of multiple memory constraints"Hal Finkel2015-03-1215-60/+42
| | | | | | | | | | | | | | | | | | | | | | | | This (r232027) has caused PR22883; so it seems those bits might be used by something else after all. Reverting until we can figure out what else to do. Original commit message: The operand flag word for ISD::INLINEASM nodes now contains a 15-bit memory constraint ID when the operand kind is Kind_Mem. This constraint ID is a numeric equivalent to the constraint code string and is converted with a target specific hook in TargetLowering. This patch maps all memory constraints to InlineAsm::Constraint_m so there is no functional change at this point. It just proves that using these previously unused bits in the encoding of the flag word doesn't break anything. The next patch will make each target preserve the current mapping of everything to Constraint_m for itself while changing the target independent implementation of the hook to return Constraint_Unknown appropriately. Each target will then be adapted in separate patches to use appropriate Constraint_* values. llvm-svn: 232093
* [X86] Fix a regression introduced by r223641.Quentin Colombet2015-03-122-2/+7
| | | | | | | | | | | | | The permps and permd instructions have their operands swapped compared to the intrinsic definition. Therefore, they do not fall into the INTR_TYPE_2OP category. I did not create a new category for those two, as they are the only one AFAICT in that case. <rdar://problem/20108262> llvm-svn: 232085
* Fix comment formatting.Eric Christopher2015-03-121-2/+1
| | | | llvm-svn: 232076
* Remove the need to cache the subtarget in the X86 TargetRegisterInfoEric Christopher2015-03-123-24/+23
| | | | | | | classes. Use a Triple instead and simplify a lot of the querying logic to use lookups on the Triple. llvm-svn: 232071
* Remove unused complex patterns for addressing modes on Hexagon.Krzysztof Parzyszek2015-03-127-611/+215
| | | | llvm-svn: 232057
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