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* Fix a crash reduced from gcc produced assembly.Rafael Espindola2010-12-071-8/+4
| | | | llvm-svn: 121085
* Second attempt at converting Thumb2's LDRpci, including updating the ↵Owen Anderson2010-12-078-72/+101
| | | | | | gazillion places that need to know about it. llvm-svn: 121082
* Sorry for such a large commit. The summary is that only MachO cares about theRafael Espindola2010-12-0710-160/+156
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | actuall addresses in a .o file, so it is better to let the MachO writer compute it. This is good for two reasons. First, areas that shouldn't care about addresses now don't have access to it. Second, the layout of each section is independent. I should use this in a subsequent commit to speed it up. Most of the patch is just removing the section address computation. The two interesting parts are the change on how we handle padding in the end of sections and how MachO can get the address of a-b when a and b are in different sections. Since now the expression evaluation normally doesn't know the section address, it will think that a-b needs relocation and let the MachO writer know. Once it has computed the section addresses, it calls back the expression evaluation with the section addresses to resolve these expressions. The remaining problem is the handling of padding. Currently it will create a special alignment fragment at the end. Since that fragment doesn't update the alignment of the section, it needs the real address to be computed. Since now the layout will not compute a-b with a and b in different sections, the only effect that the special alignment fragment has is update the address size of the section. This can also be done by the MachO writer. llvm-svn: 121076
* Add fixup for Thumb1 BL/BLX instructions.Jim Grosbach2010-12-066-17/+79
| | | | llvm-svn: 121072
* Implement jump threading of 'indirectbr' by keeping track of whether we're ↵Frits van Bommel2010-12-061-46/+80
| | | | | | looking for ConstantInt*s or BlockAddress*s. llvm-svn: 121066
* Undefined value in reg 0 may need a marker to identify end of source range.Devang Patel2010-12-061-4/+2
| | | | | | This will be used to truncate live range of DBG_VALUE instruction by register allocator and friends. llvm-svn: 121061
* If dbg_declare() or dbg_value() is not lowered by isel then emit DEBUG ↵Devang Patel2010-12-062-23/+14
| | | | | | message instead of creating DBG_VALUE for undefined value in reg0. llvm-svn: 121059
* Use references to simplify the code a bit.Rafael Espindola2010-12-063-14/+11
| | | | llvm-svn: 121050
* Adding bug fix that was suppose to be part of 121044.Wesley Peck2010-12-061-6/+6
| | | | | | patch contributed by Jack Whitham! llvm-svn: 121049
* Fixed reversed operands for IDIV and CMP instructions in MBlaze backend.Wesley Peck2010-12-061-24/+24
| | | | | | | | Use BRAD instead of BRD for indirect branches in MBlaze backend. patch contributed by Jack Whitham! llvm-svn: 121044
* Refactor ELFObjectWriter.Jason W Kim2010-12-061-216/+106
| | | | | | | + ARM/X86/MBlaze now share a common RecordRelocation + ARM/X86/MBlaze arch specific routines are limited to GetRelocType() llvm-svn: 121043
* replace a linear scan with a symtab lookup, reduce indentation.Chris Lattner2010-12-061-38/+38
| | | | | | No functionality change. llvm-svn: 121042
* use getSymbolOffset.Rafael Espindola2010-12-061-1/+1
| | | | llvm-svn: 121041
* Use a stronger predicate here, pointed out by DuncanChris Lattner2010-12-061-1/+1
| | | | llvm-svn: 121040
* add some DEBUG statements.Chris Lattner2010-12-061-3/+14
| | | | llvm-svn: 121038
* Fix a 16-bit immediate value detection bug in the MBlaze delay slot filler.Wesley Peck2010-12-061-48/+86
| | | | | | | | Address more hazards in the MBlaze delay slot filler. patch contributed by Jack Whitham! llvm-svn: 121037
* Another use of getSymbolOffset.Rafael Espindola2010-12-061-4/+8
| | | | llvm-svn: 121034
* Remove the instruction fragment to data fragment lowering since it was causingRafael Espindola2010-12-065-116/+56
| | | | | | freed data to be read. I will open a bug to track it being reenabled. llvm-svn: 121028
* Revert r121021, which broke the buildbots.Owen Anderson2010-12-062-34/+20
| | | | llvm-svn: 121026
* Trailing whitespace.Jim Grosbach2010-12-061-1/+1
| | | | llvm-svn: 121024
* Improve handling of Thumb2 PC-relative loads by converting LDRpci (and ↵Owen Anderson2010-12-062-20/+34
| | | | | | friends) to Pseudos. llvm-svn: 121021
* Encode the register operand of ARM CondCode operands correctly. ARM::CPSR ifJim Grosbach2010-12-061-2/+2
| | | | | | the instruction is predicated, reg0 otherwise. llvm-svn: 121020
* The ARM AsmMatcher needs to know that the CCOut operand is a register value,Jim Grosbach2010-12-062-1/+27
| | | | | | not an immediate. It stores either ARM::CPSR or reg0. llvm-svn: 121018
* Second try at making direct object emission produce the same resultsRafael Espindola2010-12-067-53/+18
| | | | | | | as llc + llvm-mc. This time ELF is not changed and I tested that llvm-gcc bootstrap on darwin10 using darwin9's assembler and linker. llvm-svn: 121006
* Revert previous two patches while I try to find out how to make bothRafael Espindola2010-12-063-9/+10
| | | | | | linux and darwin assemblers happy :-( llvm-svn: 121004
* Add an EmitAbsValue helper method and use it in cases where we want to be sureRafael Espindola2010-12-063-10/+9
| | | | | | | that no relocations are used (on MochO). Fixes llc producing different output from llc + llvm-mc. llvm-svn: 121000
* Fix PR8735, a really terrible problem in the inliner's "alloca merging"Chris Lattner2010-12-061-3/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | optimization. Consider: static void foo() { A = alloca ... } static void bar() { B = alloca ... call foo(); } void main() { bar() } The inliner proceeds bottom up, but lets pretend it decides not to inline foo into bar. When it gets to main, it inlines bar into main(), and says "hey, I just inlined an alloca "B" into main, lets remember that. Then it keeps going and finds that it now contains a call to foo. It decides to inline foo into main, and says "hey, foo has an alloca A, and I have an alloca B from another inlined call site, lets reuse it". The problem with this of course, is that the lifetime of A and B are nested, not disjoint. Unfortunately I can't create a reasonable testcase for this: the one in the PR is both huge and extremely sensitive, because you minor tweaks end up causing foo to get inlined into bar too early. We already have tests for the basic alloca merging optimization and this does not break them. llvm-svn: 120995
* improve commentChris Lattner2010-12-061-2/+1
| | | | llvm-svn: 120994
* improve -debug output and comments a little.Chris Lattner2010-12-061-3/+5
| | | | llvm-svn: 120993
* Support/Windows: Make MinGW happy.Michael J. Spencer2010-12-062-7/+7
| | | | llvm-svn: 120991
* Support/FileSystem: Add directory_iterator implementation.Michael J. Spencer2010-12-063-3/+94
| | | | llvm-svn: 120989
* Support/PathV2: Fix append to not add a slash to empty or root paths.Michael J. Spencer2010-12-061-1/+1
| | | | llvm-svn: 120988
* Support/Windows: Add ScopedHandle and move some clients over to it.Michael J. Spencer2010-12-062-10/+50
| | | | llvm-svn: 120987
* ptx: add shift instructionsChe-Liang Chiou2010-12-061-0/+27
| | | | llvm-svn: 120982
* Remove the getAddress getter, initialize Ordinal in the constructor and useRafael Espindola2010-12-062-1/+2
| | | | | | that on the ELF writer to detect a section we created. llvm-svn: 120981
* Simplify a bit.Rafael Espindola2010-12-061-1/+1
| | | | llvm-svn: 120980
* Use getSymbolOffset on the COFF writer.Rafael Espindola2010-12-061-1/+1
| | | | llvm-svn: 120979
* Don't use PadSectionToAlignment on windows.Rafael Espindola2010-12-061-1/+1
| | | | llvm-svn: 120978
* Add a getSymbolOffset method and use it in the ELF writer.Rafael Espindola2010-12-062-15/+13
| | | | llvm-svn: 120977
* Fix PR8728, a miscompilation I recently introduced. When optimizingChris Lattner2010-12-061-5/+62
| | | | | | | | | | | | | | | | | | | | | memcpy's like: memcpy(A, B) memcpy(A, C) we cannot delete the first memcpy as dead if A and C might be aliases. If so, we actually get: memcpy(A, B) memcpy(A, A) which is not correct to transform into: memcpy(A, A) This patch was heavily influenced by Jakub Staszak's patch in PR8728, thanks Jakub! llvm-svn: 120974
* Eliminate unneeded #include's.Evan Cheng2010-12-051-2/+0
| | | | llvm-svn: 120971
* ARM/CMakeLists.txt: Add missing MLxExpansionPass.cpp since r120960.NAKAMURA Takumi2010-12-051-0/+1
| | | | llvm-svn: 120966
* Code clean up.Evan Cheng2010-12-051-6/+6
| | | | llvm-svn: 120965
* Remove an unused variable.Evan Cheng2010-12-051-2/+1
| | | | llvm-svn: 120964
* Some cleanup before I start committing some incremental progress onCameron Zwarich2010-12-051-21/+22
| | | | | | StrongPHIElimination. llvm-svn: 120961
* Making use of VFP / NEON floating point multiply-accumulate / subtraction isEvan Cheng2010-12-0519-191/+771
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | difficult on current ARM implementations for a few reasons. 1. Even though a single vmla has latency that is one cycle shorter than a pair of vmul + vadd, a RAW hazard during the first (4? on Cortex-a8) can cause additional pipeline stall. So it's frequently better to single codegen vmul + vadd. 2. A vmla folowed by a vmul, vmadd, or vsub causes the second fp instruction to stall for 4 cycles. We need to schedule them apart. 3. A vmla followed vmla is a special case. Obvious issuing back to back RAW vmla + vmla is very bad. But this isn't ideal either: vmul vadd vmla Instead, we want to expand the second vmla: vmla vmul vadd Even with the 4 cycle vmul stall, the second sequence is still 2 cycles faster. Up to now, isel simply avoid codegen'ing fp vmla / vmls. This works well enough but it isn't the optimial solution. This patch attempts to make it possible to use vmla / vmls in cases where it is profitable. A. Add missing isel predicates which cause vmla to be codegen'ed. B. Make sure the fmul in (fadd (fmul)) has a single use. We don't want to compute a fmul and a fmla. C. Add additional isel checks for vmla, avoid cases where vmla is feeding into fp instructions (except for the #3 exceptional case). D. Add ARM hazard recognizer to model the vmla / vmls hazards. E. Add a special pre-regalloc case to expand vmla / vmls when it's likely the vmla / vmls will trigger one of the special hazards. Work in progress, only A+B are enabled. llvm-svn: 120960
* Remove the PHIElimination.h header, as it is no longer needed.Cameron Zwarich2010-12-052-82/+55
| | | | llvm-svn: 120959
* Fix PR 4170 by having ExtractValueInst::getIndexedType() reject ↵Frits van Bommel2010-12-051-7/+24
| | | | | | | | out-of-bounds indexing. Also add asserts that the indices are valid in InsertValueInst::init(). ExtractValueInst already asserts when constructed with invalid indices. llvm-svn: 120956
* I forgot to actually remove the FindCopyInsertPoint() declaration fromCameron Zwarich2010-12-051-8/+0
| | | | | | PHIElimination.h. llvm-svn: 120953
* Remove the SplitCriticalEdge() method declaration from PHIElimination.h. At oneCameron Zwarich2010-12-051-6/+0
| | | | | | | time, this method existed, but now PHIElimination uses the method of the same name on MachineBasicBlock. llvm-svn: 120952
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