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| author | Che-Liang Chiou <clchiou@gmail.com> | 2010-12-06 04:00:03 +0000 |
|---|---|---|
| committer | Che-Liang Chiou <clchiou@gmail.com> | 2010-12-06 04:00:03 +0000 |
| commit | 9f2af628a65cd6e7f06e4d9beb6bca1f5b221c01 (patch) | |
| tree | a0de3f6251c50dd3d6b80eab838f4afedc96c862 /llvm/lib | |
| parent | baf2f3b3eb3594a14f545b250302f05253fb358e (diff) | |
| download | bcm5719-llvm-9f2af628a65cd6e7f06e4d9beb6bca1f5b221c01.tar.gz bcm5719-llvm-9f2af628a65cd6e7f06e4d9beb6bca1f5b221c01.zip | |
ptx: add shift instructions
llvm-svn: 120982
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/Target/PTX/PTXInstrInfo.td | 27 |
1 files changed, 27 insertions, 0 deletions
diff --git a/llvm/lib/Target/PTX/PTXInstrInfo.td b/llvm/lib/Target/PTX/PTXInstrInfo.td index 01e0f2a2b41..ccd77df1747 100644 --- a/llvm/lib/Target/PTX/PTXInstrInfo.td +++ b/llvm/lib/Target/PTX/PTXInstrInfo.td @@ -46,6 +46,11 @@ def MEMii : Operand<i32> { // PTX Specific Node Definitions //===----------------------------------------------------------------------===// +// PTX allow generic 3-reg shifts like shl r0, r1, r2 +def PTXshl : SDNode<"ISD::SHL", SDTIntBinOp>; +def PTXsrl : SDNode<"ISD::SRL", SDTIntBinOp>; +def PTXsra : SDNode<"ISD::SRA", SDTIntBinOp>; + def PTXexit : SDNode<"PTXISD::EXIT", SDTNone, [SDNPHasChain]>; def PTXret @@ -66,6 +71,22 @@ multiclass INT3<string opcstr, SDNode opnode> { [(set RRegs32:$d, (opnode RRegs32:$a, imm:$b))]>; } +// no %type directive, non-communtable +multiclass INT3ntnc<string opcstr, SDNode opnode> { + def rr : InstPTX<(outs RRegs32:$d), + (ins RRegs32:$a, RRegs32:$b), + !strconcat(opcstr, "\t$d, $a, $b"), + [(set RRegs32:$d, (opnode RRegs32:$a, RRegs32:$b))]>; + def ri : InstPTX<(outs RRegs32:$d), + (ins RRegs32:$a, i32imm:$b), + !strconcat(opcstr, "\t$d, $a, $b"), + [(set RRegs32:$d, (opnode RRegs32:$a, imm:$b))]>; + def ir : InstPTX<(outs RRegs32:$d), + (ins i32imm:$a, RRegs32:$b), + !strconcat(opcstr, "\t$d, $a, $b"), + [(set RRegs32:$d, (opnode imm:$a, RRegs32:$b))]>; +} + multiclass PTX_LD<string opstr, RegisterClass RC, PatFrag pat_load> { def ri : InstPTX<(outs RC:$d), (ins MEMri:$a), @@ -86,6 +107,12 @@ multiclass PTX_LD<string opstr, RegisterClass RC, PatFrag pat_load> { defm ADD : INT3<"add", add>; defm SUB : INT3<"sub", sub>; +///===- Logic and Shift Instructions --------------------------------------===// + +defm SHL : INT3ntnc<"shl.b32", PTXshl>; +defm SRL : INT3ntnc<"shr.u32", PTXsrl>; +defm SRA : INT3ntnc<"shr.s32", PTXsra>; + ///===- Data Movement and Conversion Instructions -------------------------===// let neverHasSideEffects = 1 in { |
