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* [Hexagon] Add a target feature for memop generationKrzysztof Parzyszek2018-05-144-31/+32
| | | | llvm-svn: 332285
* [X86] Add NT load/store scheduler classesSimon Pilgrim2018-05-1413-84/+148
| | | | llvm-svn: 332274
* [X86] Remove and autoupgrade avx512.vbroadcast.ss/avx512.vbroadcast.sd ↵Craig Topper2018-05-142-6/+3
| | | | | | intrinsics. llvm-svn: 332271
* [X86][BtVer2] Fix MMX/YMM integer vector nt store schedulesSimon Pilgrim2018-05-141-2/+8
| | | | | | MMX was missing and YMM was tagged as a fp nt store llvm-svn: 332269
* [BranchFolding] Allow hoisting to block with a single conditional branch.Geoff Berry2018-05-141-1/+5
| | | | | | | | | | | | | | | | | | | | | Summary: The BranchFolding pass is currently missing opportunities to hoist common code if the hoisted-to block contains a single conditional branch that has register uses. This occurs somewhat frequently on AArch64 with CBZ/TBZ opcodes. This change also eliminates some code differences when debug info is present since the presence of e.g. DBG_VALUE instructions in the hoisted-to block can enable hoisting that wouldn't have occurred without them. Reviewers: MatzeB, rnk, kparzysz, twoh, aprantl, javed.absar Subscribers: kristof.beyls, JDevlieghere, mcrosier, llvm-commits Differential Revision: https://reviews.llvm.org/D46324 llvm-svn: 332265
* [Hexagon] Avoid predicate copies to integer registers from store-lockedKrzysztof Parzyszek2018-05-141-0/+15
| | | | llvm-svn: 332260
* [mips] Fix the predicates of round, ceiling, floor and trunc.Simon Dardis2018-05-142-38/+36
| | | | | | | | Reviewers: atanasyan, abeserminji, smaksimovic Differential Revision: https://reviews.llvm.org/D46691 llvm-svn: 332258
* [NFC] [Power] Fix instruction format for xsrqpiZaara Syeda2018-05-142-1/+22
| | | | | | | | | | | | xsrqpi is currently using Z23Form_1. The instruction format is xsrqpi R,VRT,VRB,RMC. Rathar than bits 11-15 being used for FRA, it should have bits 11-14 reserved and bit 15 for R. This patch adds a new class Z23Form_4 to fix the instruction format. Differential Revision: https://reviews.llvm.org/D46761 llvm-svn: 332253
* [AArch64] Improve single vector lane storesEvandro Menezes2018-05-141-20/+57
| | | | | | | | When storing the 0th lane of a vector, use a simpler and usually more efficient scalar store instead. Differential revision: https://reviews.llvm.org/D46655 llvm-svn: 332251
* [CodeGen/AccelTable]: Handle -dwarf-linkage-names=Abstract correctlyPavel Labath2018-05-143-4/+8
| | | | | | | | | | | | | | | | | | | | Summary: If we are not emitting a linkage name in the .debug_info sections, we should not add it into the index either. This makes sure our index is consistent with the actual debug info. I am also explicitly setting the --dwarf-linkage-names=All in the name-collsions test as that one would now fail on targets where this defaults to "Abstract" (in fact, it would have failed already if there wasn't a bug in the DWARF verifier, which I fix as well). Reviewers: probinson, aprantl, JDevlieghere Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D46748 llvm-svn: 332246
* [AggressiveInstCombine] avoid crashing on unsimplified code (PR37446)Sanjay Patel2018-05-141-0/+4
| | | | | | | | | This bug: https://bugs.llvm.org/show_bug.cgi?id=37446 ...raises another question: why do we run aggressive-instcombine before regular instcombine? llvm-svn: 332243
* Rename DEBUG macro to LLVM_DEBUG.Nicola Zaghen2018-05-14459-8104/+8548
| | | | | | | | | | | | | | | | The DEBUG() macro is very generic so it might clash with other projects. The renaming was done as follows: - git grep -l 'DEBUG' | xargs sed -i 's/\bDEBUG\s\?(/LLVM_DEBUG(/g' - git diff -U0 master | ../clang/tools/clang-format/clang-format-diff.py -i -p1 -style LLVM - Manual change to APInt - Manually chage DOCS as regex doesn't match it. In the transition period the DEBUG() macro is still present and aliased to the LLVM_DEBUG() one. Differential Revision: https://reviews.llvm.org/D43624 llvm-svn: 332240
* Fix "not all control paths return a value" MSVC warning. NFCI.Simon Pilgrim2018-05-141-0/+1
| | | | llvm-svn: 332238
* [AArch64][SVE] Extend parsing of Prefetch operation for SVE.Sander de Smalen2018-05-147-10/+99
| | | | | | | | | | Reviewers: rengolin, fhahn, samparker, SjoerdMeijer, javed.absar Reviewed By: fhahn Differential Revision: https://reviews.llvm.org/D46681 llvm-svn: 332234
* [mips] Correct the predicates of indexed floating point stores and loads.Simon Dardis2018-05-142-14/+14
| | | | | | | | | | Also, fix the register class for microMIPS. Reviewers: atanasyan, abeserminji, smaksimovic Differential Revision: https://reviews.llvm.org/D46689 llvm-svn: 332227
* Test commit access.Nicola Zaghen2018-05-141-1/+1
| | | | | | Remove trailing whitespace. llvm-svn: 332220
* [LLVM-C] Add Bindings For Module FlagsRobert Widmann2018-05-141-0/+104
| | | | | | | | | | | | | | | | | | | Summary: The first foray into merging debug info into the echo tests. - Add bindings to Module::getModuleFlagsMetadata() in the form of LLVMCopyModuleFlagsMetadata - Add the opaque type LLVMModuleFlagEntry to represent Module::ModuleFlagEntry - Add accessors for LLVMModuleFlagEntry's behavior, key, and metadata node. Reviewers: whitequark, deadalnix Reviewed By: whitequark Subscribers: aprantl, JDevlieghere, llvm-commits, harlanhaskins Differential Revision: https://reviews.llvm.org/D46792 llvm-svn: 332219
* Correct compatibility with the GNU Assembler's handling of comparison opsBill Wendling2018-05-141-2/+20
| | | | | | | | GAS returns -1 for a comparison operator if the result is true and 0 if false. https://www.sourceware.org/binutils/docs-2.12/as.info/Infix-Ops.html#Infix%20Ops llvm-svn: 332215
* [X86] Cleanup a multiclass that doesn't need as many parameters after recent ↵Craig Topper2018-05-141-25/+12
| | | | | | intrinsic removals. llvm-svn: 332207
* [X86] Remove and autoupgrade the cvtusi2sd intrinsic. Use ↵Craig Topper2018-05-143-8/+5
| | | | | | uitofp+insertelement instead. llvm-svn: 332206
* [X86] Add patterns for combining movss+uint_to_fp into the intrinsic ↵Craig Topper2018-05-131-0/+40
| | | | | | | | instructions under AVX512. This matches what we do for sint_to_fp. llvm-svn: 332205
* [X86] Extend instcombine folds for pclmuldq intrinsics to the 256 and 512 ↵Craig Topper2018-05-131-9/+12
| | | | | | bit version. llvm-svn: 332202
* [X86] Remove and autoupgrade masked vpermd/vpermps intrinsics.Craig Topper2018-05-133-13/+13
| | | | llvm-svn: 332198
* AMDGPU: Rename OpenCL lowering pass to be R600 specific.Matt Arsenault2018-05-134-10/+11
| | | | | | | | | | | | | | | | | | This pass is a) broken. b) r600 specific. Fixing (a) is a bit more non-trivial, but fixing (b) is easy. Move this pass to being R600 only for now. This pass does pass all the unit tests, however clang no longer generates code that looks like the unit test input, so fixing the pass requires fixing the tests and the pass as one, and checking it works with clang still. Patch by Dave Airlie llvm-svn: 332196
* AMDGPU: Make undef legal for v2i16/v2f16Matt Arsenault2018-05-131-0/+3
| | | | | | | This is apparently necessary to stop undef from being turned into a build_vector of 0s. llvm-svn: 332195
* Fixing build bot error: adding const qualifiers to std::sort lambda.Puyan Lotfi2018-05-131-1/+1
| | | | | | Errors were not reproducible on clang-6.0 on ubuntu 16.04. llvm-svn: 332192
* [NFC] MIR-Canon: switching to a stable string sorting of instructions.Puyan Lotfi2018-05-131-2/+8
| | | | llvm-svn: 332191
* [X86] Add some load folding patterns for cvtsi2ss/sd into intrinsic ↵Craig Topper2018-05-132-0/+60
| | | | | | instructions. llvm-svn: 332189
* [X86] Remove an autoupgrade legacy cvtss2sd intrinsics.Craig Topper2018-05-133-14/+12
| | | | llvm-svn: 332187
* [X86] Remove and autoupgrade cvtsi2ss/cvtsi2sd intrinsics to match what ↵Craig Topper2018-05-124-29/+24
| | | | | | clang has used for a very long time. llvm-svn: 332186
* [x86] Remove a comment obviated by r330269. Should have deleted theChandler Carruth2018-05-121-5/+0
| | | | | | | | comment in the same revision but missed it. Thanks to Dimitry Andric for catching this! llvm-svn: 332177
* Clear converters map after X86 Domain Reassignment to avoid crashesDimitry Andric2018-05-121-2/+1
| | | | | | | | | | | | | | | | | | | | | | Summary: As reported in PR37264, in some cases the X86 Domain Reassignment `runOnMachineFunction()` is called twice. Because it only deletes the `.second` members of its `InstrConverterBaseMap`, and does not clean up the map itself, this can lead to double frees and crashes. Use `DeleteContainerSeconds()` instead, so the `Converters` map can safely be reinitialized and its members re-deleted for each X86 Domain Reassignment pass. Reviewers: guyblank, craig.topper Reviewed By: craig.topper Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D46425 llvm-svn: 332176
* [NFC] Remove inaccurate commentJF Bastien2018-05-121-3/+0
| | | | | | | | | | | | | | | Summary: r271558 moved getManagedStaticMutex's mutex from a function-local static to using call_once, but left a comment added in r211424. That comment is now erroneous, remove it. Reviewers: zturner, chandlerc Subscribers: aheejin, llvm-commits Differential Revision: https://reviews.llvm.org/D46784 llvm-svn: 332175
* [X86] Add WriteFCMOV scheduler class for x87 CMOVsSimon Pilgrim2018-05-1211-16/+15
| | | | llvm-svn: 332173
* [mips] Initialize the long branch pass for testing purposesSimon Dardis2018-05-123-2/+8
| | | | llvm-svn: 332172
* [X86] Remove some unused masked conversion intrinsics that can be replaced ↵Craig Topper2018-05-122-21/+33
| | | | | | | | with an older intrinsic and a select. This is what clang already uses. llvm-svn: 332170
* Reapply "[PR16756] Use SSAUpdaterBulk in JumpThreading."Michael Zolotukhin2018-05-121-26/+30
| | | | | | | | | Stage3/stage4 bootstrap miscompares should be fixed by a non-determinism fix in IDF (r332167). This reverts commit r330446. llvm-svn: 332168
* [IDF] Enforce the returned blocks to be sorted.Michael Zolotukhin2018-05-121-5/+11
| | | | | | | | | | | | | | | | | | | | Summary: Currently the order of blocks returned by `IDF::calculate` can be non-deterministic. This was discovered in several attempts to enable SSAUpdaterBulk for JumpThreading (which led to miscompare in bootstrap between stage 3 and stage4). Originally, the blocks were put into a priority queue with a depth level as their key, and this patch adds a DFSIn number as a second key to specify a deterministic order across blocks from one level. The solution was suggested by Daniel Berlin. Reviewers: dberlin, davide Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D46646 llvm-svn: 332167
* [AMDGPU] Fix amdgpu-waves-per-eu accounting in schedulerStanislav Mekhanoshin2018-05-122-3/+7
| | | | | | | | | | We cannot query this attribute from a subtarget given a machine function. At this point attribute itself is already unavailable and can only be obtained through MFI. Differential Revision: https://reviews.llvm.org/D46781 llvm-svn: 332166
* [DAG] add convenience function to propagate FMF; NFCSanjay Patel2018-05-111-7/+1
| | | | | | | | | There's only one use of this currently, but that could change with D46563. Either way, we shouldn't have to update code outside of the flags struct when those flag definitions change. llvm-svn: 332155
* AMDGPU/GlobalISel: Implement select() for >32-bit G_STORETom Stellard2018-05-112-1/+28
| | | | | | | | | | Reviewers: arsenm, nhaehnle Subscribers: kzhuravl, wdng, yaxunl, rovka, kristof.beyls, dstuttard, tpr, llvm-commits, t-tye Differential Revision: https://reviews.llvm.org/D46153 llvm-svn: 332154
* [CodeExtractor] Allow extracting blocks with exception handlingSergey Dmitriev2018-05-111-27/+91
| | | | | | | | | | | | | | | | | This is a CodeExtractor improvement which adds support for extracting blocks which have exception handling constructs if that is legal to do. CodeExtractor performs validation checks to ensure that extraction is legal when it finds invoke instructions or EH pads (landingpad, catchswitch, or cleanuppad) in blocks to be extracted. I have also added an option to allow extraction of blocks with alloca instructions, but no validation is done for allocas. CodeExtractor caller has to validate it himself before allowing alloca instructions to be extracted. By default allocas are still not allowed in extraction blocks. Differential Revision: https://reviews.llvm.org/D45904 llvm-svn: 332151
* [DAG] clean up flag propagation for binops; NFCISanjay Patel2018-05-112-36/+22
| | | | llvm-svn: 332150
* AMDGPU/SI: Don't promote alloca to vector for AddrSpaceCast instruction.Changpeng Fang2018-05-111-1/+0
| | | | | | | | | | | | | Summary: We have no logic to promote alloca to vector for an AddrSpaceCast instruction. Reviewer: arsenm Differential Revision: https://reviews.llvm.org/D45993 llvm-svn: 332147
* [X86] Remove and autoupgrade a bunch of FMA instrinsics that are no longer ↵Craig Topper2018-05-114-34/+83
| | | | | | used by clang. llvm-svn: 332146
* [Split GEP] handle trunc() in separate-const-offset-from-gep pass.Artem Belevich2018-05-111-2/+7
| | | | | | | | | | | Let separate-const-offset-from-gep pass handle trunc() when it calculates constant offset relative to base. The pass itself may insert trunc() instructions when it canonicalises array indices to pointer-size integers and needs to handle trunc() in order to evaluate the offset. Differential Revision: https://reviews.llvm.org/D46732 llvm-svn: 332142
* [AMDGPU] Fix compilation failure when IR contains comdatYaxun Liu2018-05-111-2/+0
| | | | | | | | | | | | | | | | | Remove a useless SwitchSection which also causes compilation failure when IR contains comdat. The SwitchSection is useless because the current section is already correct text section for the function therefore no need to switch. It causes compilation failure for comdat because functions with comdat has specific text section, not the default .text section. Since HIP uses comdat, this bug caused failures for HIP. Differential Revision: https://reviews.llvm.org/D46770 llvm-svn: 332137
* [DAG] reduce code duplication; NFCISanjay Patel2018-05-111-8/+7
| | | | llvm-svn: 332133
* [InstCombine] Handle atomic memset in the same way as regular memsetDaniel Neilson2018-05-112-4/+6
| | | | | | | | | | | | | | | | | | Summary: This change adds handling of the atomic memset intrinsic to the code path that simplifies the regular memset. In practice this means that we will now also expand a small constant-length atomic memset into a single unordered atomic store. Reviewers: apilipenko, skatkov, mkazantsev, anna, reames Reviewed By: reames Subscribers: reames, llvm-commits Differential Revision: https://reviews.llvm.org/D46660 llvm-svn: 332132
* [DAGCombiner] Set the right SDLoc on extended SETCC uses (7/N)Vedant Kumar2018-05-111-19/+13
| | | | | | | | | | | | | | | | | | | | ExtendSetCCUses updates SETCC nodes which use a load (OriginalLoad) to reflect a simplification to the load (ExtLoad). Based on my reading, ExtendSetCCUses may create new nodes to extend a constant attached to a SETCC. It also creates fresh SETCC nodes which refer to any updated operands. ISTM that the location applied to the new constant and SETCC nodes should be the same as the location of the ExtLoad. This was suggested by Adrian in https://reviews.llvm.org/D45995. Part of: llvm.org/PR37262 Differential Revision: https://reviews.llvm.org/D46216 llvm-svn: 332119
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