diff options
| author | Craig Topper <craig.topper@intel.com> | 2018-05-13 01:54:33 +0000 |
|---|---|---|
| committer | Craig Topper <craig.topper@intel.com> | 2018-05-13 01:54:33 +0000 |
| commit | 38b713d4a7daa8eab7d4c76398c6ceb91b64229d (patch) | |
| tree | 47e2f8b47eeb0809e6288bdd953b4b78078bec0e /llvm/lib | |
| parent | 28b85caea8f65790c82bb06ad212f9189565de5f (diff) | |
| download | bcm5719-llvm-38b713d4a7daa8eab7d4c76398c6ceb91b64229d.tar.gz bcm5719-llvm-38b713d4a7daa8eab7d4c76398c6ceb91b64229d.zip | |
[X86] Add some load folding patterns for cvtsi2ss/sd into intrinsic instructions.
llvm-svn: 332189
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/Target/X86/X86InstrAVX512.td | 20 | ||||
| -rw-r--r-- | llvm/lib/Target/X86/X86InstrSSE.td | 40 |
2 files changed, 60 insertions, 0 deletions
diff --git a/llvm/lib/Target/X86/X86InstrAVX512.td b/llvm/lib/Target/X86/X86InstrAVX512.td index 81b4a2adf02..94617bc7de6 100644 --- a/llvm/lib/Target/X86/X86InstrAVX512.td +++ b/llvm/lib/Target/X86/X86InstrAVX512.td @@ -6938,9 +6938,19 @@ def : Pat<(v4f32 (X86Movss def : Pat<(v4f32 (X86Movss (v4f32 VR128X:$dst), + (v4f32 (scalar_to_vector (f32 (sint_to_fp (loadi64 addr:$src))))))), + (VCVTSI642SSZrm_Int VR128X:$dst, addr:$src)>; + +def : Pat<(v4f32 (X86Movss + (v4f32 VR128X:$dst), (v4f32 (scalar_to_vector (f32 (sint_to_fp GR32:$src)))))), (VCVTSI2SSZrr_Int VR128X:$dst, GR32:$src)>; +def : Pat<(v4f32 (X86Movss + (v4f32 VR128X:$dst), + (v4f32 (scalar_to_vector (f32 (sint_to_fp (loadi32 addr:$src))))))), + (VCVTSI2SSZrm_Int VR128X:$dst, addr:$src)>; + def : Pat<(v2f64 (X86Movsd (v2f64 VR128X:$dst), (v2f64 (scalar_to_vector (f64 (sint_to_fp GR64:$src)))))), @@ -6948,8 +6958,18 @@ def : Pat<(v2f64 (X86Movsd def : Pat<(v2f64 (X86Movsd (v2f64 VR128X:$dst), + (v2f64 (scalar_to_vector (f64 (sint_to_fp (loadi64 addr:$src))))))), + (VCVTSI642SDZrm_Int VR128X:$dst, addr:$src)>; + +def : Pat<(v2f64 (X86Movsd + (v2f64 VR128X:$dst), (v2f64 (scalar_to_vector (f64 (sint_to_fp GR32:$src)))))), (VCVTSI2SDZrr_Int VR128X:$dst, GR32:$src)>; + +def : Pat<(v2f64 (X86Movsd + (v2f64 VR128X:$dst), + (v2f64 (scalar_to_vector (f64 (sint_to_fp (loadi32 addr:$src))))))), + (VCVTSI2SDZrm_Int VR128X:$dst, addr:$src)>; } // Predicates = [HasAVX512] // Convert float/double to signed/unsigned int 32/64 with truncation diff --git a/llvm/lib/Target/X86/X86InstrSSE.td b/llvm/lib/Target/X86/X86InstrSSE.td index 71eebcfa97d..c25b95d1e5a 100644 --- a/llvm/lib/Target/X86/X86InstrSSE.td +++ b/llvm/lib/Target/X86/X86InstrSSE.td @@ -1410,9 +1410,19 @@ def : Pat<(v4f32 (X86Movss def : Pat<(v4f32 (X86Movss (v4f32 VR128:$dst), + (v4f32 (scalar_to_vector (f32 (sint_to_fp (loadi64 addr:$src))))))), + (VCVTSI642SSrm_Int VR128:$dst, addr:$src)>; + +def : Pat<(v4f32 (X86Movss + (v4f32 VR128:$dst), (v4f32 (scalar_to_vector (f32 (sint_to_fp GR32:$src)))))), (VCVTSI2SSrr_Int VR128:$dst, GR32:$src)>; +def : Pat<(v4f32 (X86Movss + (v4f32 VR128:$dst), + (v4f32 (scalar_to_vector (f32 (sint_to_fp (loadi32 addr:$src))))))), + (VCVTSI2SSrm_Int VR128:$dst, addr:$src)>; + def : Pat<(v2f64 (X86Movsd (v2f64 VR128:$dst), (v2f64 (scalar_to_vector (f64 (sint_to_fp GR64:$src)))))), @@ -1420,8 +1430,18 @@ def : Pat<(v2f64 (X86Movsd def : Pat<(v2f64 (X86Movsd (v2f64 VR128:$dst), + (v2f64 (scalar_to_vector (f64 (sint_to_fp (loadi64 addr:$src))))))), + (VCVTSI642SDrm_Int VR128:$dst, addr:$src)>; + +def : Pat<(v2f64 (X86Movsd + (v2f64 VR128:$dst), (v2f64 (scalar_to_vector (f64 (sint_to_fp GR32:$src)))))), (VCVTSI2SDrr_Int VR128:$dst, GR32:$src)>; + +def : Pat<(v2f64 (X86Movsd + (v2f64 VR128:$dst), + (v2f64 (scalar_to_vector (f64 (sint_to_fp (loadi32 addr:$src))))))), + (VCVTSI2SDrm_Int VR128:$dst, addr:$src)>; } // Predicates = [UseAVX] let Predicates = [UseSSE2] in { @@ -1444,8 +1464,18 @@ def : Pat<(v2f64 (X86Movsd def : Pat<(v2f64 (X86Movsd (v2f64 VR128:$dst), + (v2f64 (scalar_to_vector (f64 (sint_to_fp (loadi64 addr:$src))))))), + (CVTSI642SDrm_Int VR128:$dst, addr:$src)>; + +def : Pat<(v2f64 (X86Movsd + (v2f64 VR128:$dst), (v2f64 (scalar_to_vector (f64 (sint_to_fp GR32:$src)))))), (CVTSI2SDrr_Int VR128:$dst, GR32:$src)>; + +def : Pat<(v2f64 (X86Movsd + (v2f64 VR128:$dst), + (v2f64 (scalar_to_vector (f64 (sint_to_fp (loadi32 addr:$src))))))), + (CVTSI2SDrm_Int VR128:$dst, addr:$src)>; } // Predicates = [UseSSE2] let Predicates = [UseSSE1] in { @@ -1456,8 +1486,18 @@ def : Pat<(v4f32 (X86Movss def : Pat<(v4f32 (X86Movss (v4f32 VR128:$dst), + (v4f32 (scalar_to_vector (f32 (sint_to_fp (loadi64 addr:$src))))))), + (CVTSI642SSrm_Int VR128:$dst, addr:$src)>; + +def : Pat<(v4f32 (X86Movss + (v4f32 VR128:$dst), (v4f32 (scalar_to_vector (f32 (sint_to_fp GR32:$src)))))), (CVTSI2SSrr_Int VR128:$dst, GR32:$src)>; + +def : Pat<(v4f32 (X86Movss + (v4f32 VR128:$dst), + (v4f32 (scalar_to_vector (f32 (sint_to_fp (loadi32 addr:$src))))))), + (CVTSI2SSrm_Int VR128:$dst, addr:$src)>; } // Predicates = [UseSSE1] let Predicates = [HasAVX, NoVLX] in { |
