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* move this over to the dagAndrew Lenharth2005-12-052-10/+9
| | | | llvm-svn: 24609
* getRawValue zero extens for unsigned values, use getsextvalue so that weChris Lattner2005-12-051-3/+3
| | | | | | | know that small negative values fit into the immediate field of addressing modes. llvm-svn: 24608
* fix constant pool loadsAndrew Lenharth2005-12-051-1/+1
| | | | llvm-svn: 24607
* Fix the #1 code quality problem that I have seen on X86 (and it also affectsChris Lattner2005-12-051-6/+162
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | PPC and other targets). In a particular, consider code like this: struct Vector3 { double x, y, z; }; struct Matrix3 { Vector3 a, b, c; }; double dot(Vector3 &a, Vector3 &b) { return a.x * b.x + a.y * b.y + a.z * b.z; } Vector3 mul(Vector3 &a, Matrix3 &b) { Vector3 r; r.x = dot( a, b.a ); r.y = dot( a, b.b ); r.z = dot( a, b.c ); return r; } void transform(Matrix3 &m, Vector3 *x, int n) { for (int i = 0; i < n; i++) x[i] = mul( x[i], m ); } we compile transform to a loop with all of the GEP instructions for indexing into 'm' pulled out of the loop (9 of them). Because isel occurs a bb at a time we are unable to fold the constant index into the loads in the loop, leading to PPC code that looks like this: LBB3_1: ; no_exit.preheader li r2, 0 addi r6, r3, 64 ;; 9 values live across the loop body! addi r7, r3, 56 addi r8, r3, 48 addi r9, r3, 40 addi r10, r3, 32 addi r11, r3, 24 addi r12, r3, 16 addi r30, r3, 8 LBB3_2: ; no_exit lfd f0, 0(r30) lfd f1, 8(r4) fmul f0, f1, f0 lfd f2, 0(r3) ;; no constant indices folded into the loads! lfd f3, 0(r4) lfd f4, 0(r10) lfd f5, 0(r6) lfd f6, 0(r7) lfd f7, 0(r8) lfd f8, 0(r9) lfd f9, 0(r11) lfd f10, 0(r12) lfd f11, 16(r4) fmadd f0, f3, f2, f0 fmul f2, f1, f4 fmadd f0, f11, f10, f0 fmadd f2, f3, f9, f2 fmul f1, f1, f6 stfd f0, 0(r4) fmadd f0, f11, f8, f2 fmadd f1, f3, f7, f1 stfd f0, 8(r4) fmadd f0, f11, f5, f1 addi r29, r4, 24 stfd f0, 16(r4) addi r2, r2, 1 cmpw cr0, r2, r5 or r4, r29, r29 bne cr0, LBB3_2 ; no_exit uh, yuck. With this patch, we now sink the constant offsets into the loop, producing this code: LBB3_1: ; no_exit.preheader li r2, 0 LBB3_2: ; no_exit lfd f0, 8(r3) lfd f1, 8(r4) fmul f0, f1, f0 lfd f2, 0(r3) lfd f3, 0(r4) lfd f4, 32(r3) ;; much nicer. lfd f5, 64(r3) lfd f6, 56(r3) lfd f7, 48(r3) lfd f8, 40(r3) lfd f9, 24(r3) lfd f10, 16(r3) lfd f11, 16(r4) fmadd f0, f3, f2, f0 fmul f2, f1, f4 fmadd f0, f11, f10, f0 fmadd f2, f3, f9, f2 fmul f1, f1, f6 stfd f0, 0(r4) fmadd f0, f11, f8, f2 fmadd f1, f3, f7, f1 stfd f0, 8(r4) fmadd f0, f11, f5, f1 addi r6, r4, 24 stfd f0, 16(r4) addi r2, r2, 1 cmpw cr0, r2, r5 or r4, r6, r6 bne cr0, LBB3_2 ; no_exit This is much nicer as it reduces register pressure in the loop a lot. On X86, this takes the function from having 9 spilled registers to 2. This should help some spec programs on X86 (gzip?) This is currently only enabled with -enable-gep-isel-opt to allow perf testing tonight. llvm-svn: 24606
* Add a flag to Module::getGlobalVariable to allow it to return vars withChris Lattner2005-12-051-7/+7
| | | | | | | | internal linkage. Patch provided by Evan Jones, thanks! llvm-svn: 24604
* Wrap a long line, never internalize llvm.used.Chris Lattner2005-12-051-2/+6
| | | | llvm-svn: 24602
* Several things:Chris Lattner2005-12-051-24/+32
| | | | | | | | | | | | | 1. Remove redundant type casts now that PR673 is implemented. 2. Implement the OUT*ir instructions correctly. The port number really *is* a 16-bit value, but the patterns should only match if the number is 0-255. Update the patterns so they now match. 3. Fix patterns for shifts to reflect that the shift amount is always an i8, not an i16 as they were believed to be before. This previous fib stopped working when we started knowing that CL has type i8. 4. Change use of i16i8imm in SH*ri patterns to all be imm. llvm-svn: 24599
* On some targets (e.g. X86), shift amounts are not the same as the valueChris Lattner2005-12-051-3/+6
| | | | | | being shifted. Don't assume they are. llvm-svn: 24598
* Add some explicit type casts so that tblgen knows the type of the ↵Chris Lattner2005-12-051-6/+6
| | | | | | shiftamount, which is not necessarily the same as the type being shifted. llvm-svn: 24595
* Add some explicit type casts so that tblgen knows the type of the shiftChris Lattner2005-12-051-5/+5
| | | | | | amount, which is not necessarily the same as the type being shifted. llvm-svn: 24594
* The basic fneg cases are already autogen'dChris Lattner2005-12-041-4/+2
| | | | llvm-svn: 24592
* Autogen matching code for ADJCALLSTACK[UP|DOWN], thanks to Evan's tblgenChris Lattner2005-12-042-11/+12
| | | | | | improvements. llvm-svn: 24591
* Finish moving uncond br over to .td file, remove from .cpp file.Chris Lattner2005-12-042-4/+2
| | | | llvm-svn: 24590
* Define BR in the .td file now that Evan made tblgen smarter.Chris Lattner2005-12-042-5/+10
| | | | llvm-svn: 24589
* Added isel patterns for RET, JMP, and WRITEPORT.Evan Cheng2005-12-041-39/+53
| | | | llvm-svn: 24588
* * Added instruction property hasCtrlDep for those which r/w control-flowEvan Cheng2005-12-042-3/+27
| | | | | | | | | | | chains. * Added DAG node property SDNPHasChain for nodes which r/w control-flow chains. * Renamed SDTVT to SDTOther. * Added several new SDTypeProfiles for BR, BRCOND, RET, and WRITEPORT. * Added SDNode definitions for BR, BRCOND, RET, and WRITEPORT. llvm-svn: 24586
* Fix PR672 another way which should be more robustChris Lattner2005-12-041-16/+14
| | | | llvm-svn: 24585
* dbg.stoppoint returns a value, don't forget to init itChris Lattner2005-12-031-0/+1
| | | | llvm-svn: 24583
* Fix SimplifyCFG/2005-12-03-IncorrectPHIFold.llChris Lattner2005-12-031-8/+14
| | | | llvm-svn: 24581
* Fix test/Regression/ExecutionEngine/2005-12-02-TailCallBug.ll and PR672.Chris Lattner2005-12-031-0/+14
| | | | | | | | This also fixes 177.mesa, the only program that fails with --enable-x86-fastcc turned on. Given a clean nightly tester run, we should be able to turn it on by default! llvm-svn: 24578
* bah, must generate all resultsAndrew Lenharth2005-12-021-2/+8
| | | | llvm-svn: 24574
* cycle counter fixAndrew Lenharth2005-12-021-0/+6
| | | | llvm-svn: 24573
* add a noteChris Lattner2005-12-021-0/+6
| | | | llvm-svn: 24572
* Don't remove two operand, two result nodes from the binary ops map. TheseChris Lattner2005-12-011-36/+39
| | | | | | | | should come from the arbitrary ops map. This fixes Regression/CodeGen/PowerPC/2005-12-01-Crash.ll llvm-svn: 24571
* Promote line and column number information for our friendly 64-bit targets.Chris Lattner2005-12-011-3/+10
| | | | llvm-svn: 24568
* IA64 doesn't support the LOCATION node, and for some reason the ISelPatternChris Lattner2005-12-011-0/+3
| | | | | | stuff isn't using ISelLowering.cpp llvm-svn: 24567
* Make sure these get added into the codegenmap when appropriateChris Lattner2005-12-011-4/+5
| | | | llvm-svn: 24566
* This is a bugfix for SelectNodeTo. In certain situations, we could beChris Lattner2005-12-011-0/+110
| | | | | | | | | | selecting a node and use a mix of getTargetNode() and SelectNodeTo. Because SelectNodeTo didn't check the CSE maps for a preexisting node and didn't insert its result into the CSE maps, we would sometimes miss a CSE opportunity. This is extremely rare, but worth fixing for completeness. llvm-svn: 24565
* major think-oAndrew Lenharth2005-12-011-5/+10
| | | | llvm-svn: 24564
* Support multiple ValueTypes per RegisterClass, needed for upcoming vectorNate Begeman2005-12-0110-35/+46
| | | | | | work. This change has no effect on generated code. llvm-svn: 24563
* Cosmetic change, better reflects actual valuesNate Begeman2005-12-011-6/+5
| | | | llvm-svn: 24562
* Fix a regression caused by a patch earlier todayChris Lattner2005-12-011-1/+2
| | | | llvm-svn: 24561
* Flags where I think I need them, quick, before the nightly tester startsAndrew Lenharth2005-12-011-23/+42
| | | | llvm-svn: 24560
* Proper support for shifts with register shift value.Evan Cheng2005-12-012-44/+24
| | | | llvm-svn: 24559
* Use a getCopyToReg() variant to generate a flaggy CopyToReg node.Evan Cheng2005-12-011-8/+2
| | | | llvm-svn: 24558
* SelectNodeTo now returns its result, we must pay attention to it.Chris Lattner2005-11-301-40/+29
| | | | llvm-svn: 24552
* Pay attn to the node returned by SelectNodeToChris Lattner2005-11-301-37/+28
| | | | llvm-svn: 24551
* SelectNodeTo now returns its result, we must pay attention to it.Chris Lattner2005-11-301-20/+18
| | | | llvm-svn: 24550
* SelectNodeTo now returns N. Use it instead of return N directly.Chris Lattner2005-11-301-108/+81
| | | | llvm-svn: 24549
* Make SelectNodeTo return NChris Lattner2005-11-301-35/+49
| | | | llvm-svn: 24548
* Fix Regression/CodeGen/PowerPC/2005-11-30-vastart-crash.llChris Lattner2005-11-301-2/+6
| | | | llvm-svn: 24547
* Fix a bug where we didn't realize that vaarg reads memory. This fixesChris Lattner2005-11-301-0/+7
| | | | | | Transforms/DeadStoreElimination/2005-11-30-vaarg.ll llvm-svn: 24545
* Fix a typo in my latest changeNate Begeman2005-11-301-2/+2
| | | | llvm-svn: 24542
* No longer track value types for asm printer operands, and remove them asNate Begeman2005-11-308-89/+92
| | | | | | | an argument to every operand printing function. Requires some slight tweaks to x86, the only user. llvm-svn: 24541
* CALLSEQ_START/END nodes don't get memoized, do not add them in whenChris Lattner2005-11-301-0/+4
| | | | | | replaceAllUses'ing. llvm-svn: 24539
* remove redundant codeAndrew Lenharth2005-11-301-14/+2
| | | | llvm-svn: 24538
* At long last, you can say that f32 isn't supported for setccAndrew Lenharth2005-11-301-1/+28
| | | | llvm-svn: 24537
* Make typesafe that which isn't: FCMOVxxAndrew Lenharth2005-11-304-26/+52
| | | | llvm-svn: 24536
* FPSelect and more custom loweringAndrew Lenharth2005-11-305-25/+69
| | | | llvm-svn: 24535
* First chunk of actually generating vector code for packed types. TheseNate Begeman2005-11-302-13/+63
| | | | | | | | | | | | | | | | | | | | | | | changes allow us to generate the following code: _foo: li r2, 0 lvx v0, r2, r3 vaddfp v0, v0, v0 stvx v0, r2, r3 blr for this llvm: void %foo(<4 x float>* %a) { entry: %tmp1 = load <4 x float>* %a %tmp2 = add <4 x float> %tmp1, %tmp1 store <4 x float> %tmp2, <4 x float>* %a ret void } llvm-svn: 24534
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