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| author | Nate Begeman <natebegeman@mac.com> | 2005-12-01 04:48:26 +0000 |
|---|---|---|
| committer | Nate Begeman <natebegeman@mac.com> | 2005-12-01 04:48:26 +0000 |
| commit | aa5f8f2a262857da781e23fe919e374e98a0151a (patch) | |
| tree | 35179f8e9ef10bb30adb63a03dbacbaf828cb1e3 /llvm/lib | |
| parent | bd099102f053542318e897dc088b7662cd1ee330 (diff) | |
| download | bcm5719-llvm-aa5f8f2a262857da781e23fe919e374e98a0151a.tar.gz bcm5719-llvm-aa5f8f2a262857da781e23fe919e374e98a0151a.zip | |
Cosmetic change, better reflects actual values
llvm-svn: 24562
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/Target/PowerPC/PPCRegisterInfo.td | 11 |
1 files changed, 5 insertions, 6 deletions
diff --git a/llvm/lib/Target/PowerPC/PPCRegisterInfo.td b/llvm/lib/Target/PowerPC/PPCRegisterInfo.td index c4ec815c17b..d62045d8103 100644 --- a/llvm/lib/Target/PowerPC/PPCRegisterInfo.td +++ b/llvm/lib/Target/PowerPC/PPCRegisterInfo.td @@ -28,8 +28,8 @@ class GP8<GPR Alias> : PPCReg<Alias.Name> { } // SPR - One of the 32-bit special-purpose registers -class SPR<bits<5> num, string n> : PPCReg<n> { - field bits<5> Num = num; +class SPR<bits<10> num, string n> : PPCReg<n> { + field bits<10> Num = num; } // FPR - One of the 32 64-bit floating-point registers @@ -126,12 +126,11 @@ def CR4 : CR<4, "cr4">; def CR5 : CR<5, "cr5">; def CR6 : CR<6, "cr6">; def CR7 : CR<7, "cr7">; // Link register -// FIXME: encode actual spr numbers here -def LR : SPR<2, "lr">; +def LR : SPR<8, "lr">; // Count register -def CTR : SPR<3, "ctr">; +def CTR : SPR<9, "ctr">; // VRsave register -def VRSAVE: SPR<4, "VRsave">; +def VRSAVE: SPR<256, "VRsave">; /// Register classes // Allocate volatiles first |
