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* [X86] Optimize v2i32/v2f32 scatters.Craig Topper2018-01-112-30/+58
| | | | | | | | If the index is v2i64 we can use the scatter instruction that has v4i32/v4f32 data register, v2i64 index, and v2i1 mask. Similar was already done for gather. Implement custom widening for v2i32 data to remove the code that reverses type legalization during lowering. llvm-svn: 322254
* [DWARF][NFC] Overload AsmPrinter::emitDwarfStringOffsets() to take a ↵Wolfgang Pieb2018-01-111-3/+4
| | | | | | | | | | DwarfStringPoolEntry record. Differential Revision: https://reviews.llvm.org/D41920 llvm-svn: 322250
* [NFC] Commit to mention that r322248 is actually made by AndrewScheideckerMarcello Maggioni2018-01-111-1/+1
| | | | llvm-svn: 322249
* [SimplifyCFG] Add cut-off for InitializeUniqueCases.Marcello Maggioni2018-01-111-13/+25
| | | | | | | | | | | | | The function can take a significant amount of time on some complicated test cases, but for the currently only use of the function we can stop the initialization much earlier when we find out we are going to discard the result anyway in the caller of the function. Adding configurable cut-off points so that we avoid wasting time. NFCI. llvm-svn: 322248
* Revert "AArch64: Fix emergency spillslot being out of reach for large ↵Matthias Braun2018-01-108-57/+11
| | | | | | | | | | | | callframes" Revert for now as the testcase is hitting a pre-existing verifier error that manifest as a failure when expensive checks are enabled (or -verify-machineinstrs) is used. This reverts commit r322200. llvm-svn: 322231
* LiveRangeEdit: Inline markDeadRemat() into only user; NFCMatthias Braun2018-01-101-1/+1
| | | | | | | This function was only called from a single place in which we didn't even need the `if (DeadRemats)` check. llvm-svn: 322230
* [X86] Move HasNOPL to a subtarget feature bit. Plumb MCSubtargetInfo through ↵Craig Topper2018-01-104-57/+79
| | | | | | | | | | the MCAsmBackend constructor After D41349, we can no get a MCSubtargetInfo into the MCAsmBackend constructor. This allows us to get NOPL from a subtarget feature rather than a CPU name blacklist. Differential Revision: https://reviews.llvm.org/D41721 llvm-svn: 322227
* LiveRangeEdit: Simplify code; NFCMatthias Braun2018-01-101-12/+14
| | | | | | | | Simplify the code slightly: Instead of creating empty subranges in one case and immediately removing them, do not create them in the first place. llvm-svn: 322226
* [RISCV] Implement support for the BranchRelaxation passAlex Bradbury2018-01-105-9/+133
| | | | | | | | | Branch relaxation is needed to support branch displacements that overflow the instruction's immediate field. Differential Revision: https://reviews.llvm.org/D40830 llvm-svn: 322224
* TargetLoweringBase: The ios simulator has no bzero function.Matthias Braun2018-01-101-3/+12
| | | | | | | | Make sure I really get back to the beahvior before my rewrite in r321035 which turned out not to be completely NFC as I changed the behavior for the ios simulator environment. llvm-svn: 322223
* [RISCV] Implement branch analysisAlex Bradbury2018-01-102-0/+182
| | | | | | | | | This is a prerequisite for the branch relaxation pass, and allows a number of optimisation passes (e.g. BranchFolding and MachineBlockPlacement) to work. Differential Revision: https://reviews.llvm.org/D40808 llvm-svn: 322222
* [RISCV] Add support for llvm.{frameaddress,returnaddress} intrinsicsAlex Bradbury2018-01-102-0/+59
| | | | llvm-svn: 322218
* [RISCV] Add basic support for inline asm constraintsAlex Bradbury2018-01-104-0/+96
| | | | llvm-svn: 322217
* [RISCV] Support stack frames and offsets up to 32-bitsAlex Bradbury2018-01-105-11/+79
| | | | | | Differential Revision: https://reviews.llvm.org/D40807 llvm-svn: 322216
* [RISCV] Support for varargsAlex Bradbury2018-01-104-24/+183
| | | | | | | | | | | | Includes support for expanding va_copy. Also adds support for using 'aligned' registers when necessary for vararg calls, and ensure the frame pointer always points to the bottom of the vararg spill region. This is necessary to ensure that the saved return address and stack pointer are always available at fixed known offsets of the frame pointer. Differential Revision: https://reviews.llvm.org/D40805 llvm-svn: 322215
* Test commit accessScott Linder2018-01-101-2/+2
| | | | llvm-svn: 322213
* [SelectionDAG][X86] Explicitly store the scale in the gather/scatter ISD nodesCraig Topper2018-01-108-40/+66
| | | | | | | | | | Currently we infer the scale at isel time by analyzing whether the base is a constant 0 or not. If it is we assume scale is 1, else we take it from the element size of the pass thru or stored value. This seems a little weird and I think it makes more sense to make it explicit in the DAG rather than doing tricky things in the backend. Most of this patch is just making sure we copy the scale around everywhere. Differential Revision: https://reviews.llvm.org/D40055 llvm-svn: 322210
* [MachineOutliner] Outline ADRPsJessica Paquette2018-01-101-0/+6
| | | | | | | | | ADRP instructions weren't being outlined because they're PC-relative and thus fail the LR checks. This patch adds a special case for ADRPs to getOutliningType to make sure that ADRPs can be outlined and updates the MIR test. llvm-svn: 322207
* AArch64: Fix emergency spillslot being out of reach for large callframesMatthias Braun2018-01-108-11/+57
| | | | | | | | | | | | | | | | | | | | | | | | | | | Large callframes (calls with several hundreds or thousands or parameters) could lead to situations in which the emergency spillslot is out of range to be addressed relative to the stack pointer. This commit forces the use of a frame pointer in the presence of large callframes. This commit does several things: - Compute max callframe size at the end of instruction selection. - Add mirFileLoaded target callback. Use it to compute the max callframe size after loading a .mir file when the size wasn't specified in the file. - Let TargetFrameLowering::hasFP() return true if there exists a callframe > 255 bytes. - Always place the emergency spillslot close to FP if we have a frame pointer. - Note that `useFPForScavengingIndex()` would previously return false when a base pointer was available leading to the emergency spillslot getting allocated late (that's the whole effect of this callback). Which made no sense to me so I took this case out: Even though the emergency spillslot is technically not referenced by FP in this case we still want it allocated early. Differential Revision: https://reviews.llvm.org/D40876 llvm-svn: 322200
* [X86][MMX] Pull out common MMX VT test. NFCI.Simon Pilgrim2018-01-101-28/+27
| | | | llvm-svn: 322195
* [AMDGPU][MC][GFX8][GFX9] Added XNACK_MASK supportDmitry Preobrazhensky2018-01-108-5/+54
| | | | | | | | | See bug 35764: https://bugs.llvm.org/show_bug.cgi?id=35764 Differential Revision: https://reviews.llvm.org/D41614 Reviewers: vpykhtin, artem.tamazov, arsenm llvm-svn: 322189
* Avoid inlining if there is byval arguments with non-alloca address spaceBjorn Pettersson2018-01-101-0/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: After teaching InlineCost more about address spaces () another fault was detected in the inliner. If an argument has the byval attribute the parameter might be copied to an alloca. That part seems to work fine even if the argument has a different address space than the alloca address space. However, if the address spaces differ, then the inlined function still might refer to the parameter using the original address space (the inliner does not handle that situation very well). This patch avoids the problem by simply disallowing inlining when there are byval arguments with address space that differs from the alloca address space. I'm not really sure how to transform the code if we want to get inlining for this situation. I assume that it never has been working, and that the fixes in r321809 just exposed an old problem. Fault found by skatkov (Serguei Katkov). It is mentioned in follow up comments to https://reviews.llvm.org/D40455. Reviewers: skatkov Reviewed By: skatkov Subscribers: uabelho, eraman, llvm-commits, haicheng Differential Revision: https://reviews.llvm.org/D41898 llvm-svn: 322181
* [AArch64][SVE] Asm: Add support for (mov|dup) of scalarSander de Smalen2018-01-102-0/+37
| | | | | | | | | | | | | | Summary: This patch adds support for 'dup' (Scalar -> SVE) and its corresponding 'mov' alias. Reviewers: fhahn, rengolin, evandro, echristo Reviewed By: fhahn Subscribers: aemerson, javed.absar, tschuett, kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D41822 llvm-svn: 322172
* [ARM GlobalISel] Map G_FNEG to the FPR bankDiana Picus2018-01-101-1/+2
| | | | llvm-svn: 322169
* [ARM GlobalISel] Legalize G_FNEG for s32 and s64Diana Picus2018-01-101-1/+2
| | | | | | | | | | | | | For hard float, it is legal. For soft float, we need to lower to 0 - x first, and then we can use the libcall for G_FSUB. This is undoing some of the canonicalization performed by the IRTranslator (which introduces G_FNEG when it sees a 0 - x). Ideally, that canonicalization would be performed by a pre-legalizer pass that would allow targets to opt out of this behaviour rather than dance around it in the legalizer. llvm-svn: 322168
* [TableGen][AsmMatcherEmitter] Generate assembler checks for tied operandsSander de Smalen2018-01-101-0/+3
| | | | | | | | | | | | | | | | | | | | Summary: This extends TableGen's AsmMatcherEmitter with code that generates a table with tied-operand constraints. The constraints are checked when parsing the instruction. If an operand is not equal to its tied operand, the assembler will give an error. Patch [2/3] in a series to add operand constraint checks for SVE's predicated ADD/SUB. Reviewers: olista01, rengolin, mcrosier, fhahn, craig.topper, evandro, echristo Reviewed By: fhahn Subscribers: javed.absar, llvm-commits Differential Revision: https://reviews.llvm.org/D41446 llvm-svn: 322166
* Temporarily revertJonas Paulsson2018-01-101-25/+15
| | | | | | | | "[SystemZ] Check for legality before doing LOAD AND TEST transformations." , due to test failures. llvm-svn: 322165
* [ARM GlobalISel] Legalize s32/s64 G_FCONSTANTDiana Picus2018-01-101-3/+14
| | | | | | | | Legal for hard float. Change to G_CONSTANT for soft float (but preserve the binary representation). llvm-svn: 322164
* [SelectionDAGBuilder] Chain prefetches less aggressively.Jonas Paulsson2018-01-101-7/+13
| | | | | | | | | | | | | Prefetches used to always be chained between any previous and following memory accesses. The problem with this was that later optimizations, such as folding of a load into the user instruction, got disrupted. This patch relaxes the chaining of prefetches in order to remedy this. Reveiw: Hal Finkel https://reviews.llvm.org/D38886 llvm-svn: 322163
* [ARM GlobalISel] Legalize G_CONSTANT for scalars > 32 bitsDiana Picus2018-01-101-3/+4
| | | | | | Make G_CONSTANT narrow for any scalars larger than 32 bits. llvm-svn: 322162
* [SystemZ] Check for legality before doing LOAD AND TEST transformations.Jonas Paulsson2018-01-101-15/+25
| | | | | | | | | | Since a load and test instruction treat its operands as signed, it can only replace a logical compare for EQ/NE uses. Review: Ulrich Weigand https://bugs.llvm.org/show_bug.cgi?id=35662 llvm-svn: 322161
* [ExecutionEngine] Remove an unused variable.Lang Hames2018-01-101-1/+0
| | | | | | | Patch by Evgeniy Tyurin. Thanks Evgeniy! Review: https://reviews.llvm.org/D41431 llvm-svn: 322158
* Add explanatory comment to LoadStoreVectorizer.Justin Lebar2018-01-101-0/+32
| | | | | | | | | | Reviewers: arsenm Subscribers: rengolin, sanjoy, wdng, hiraditya, asbirlea Differential Revision: https://reviews.llvm.org/D41890 llvm-svn: 322157
* [MIR] Repurposing '$' sigil used by external symbols. Replacing with '&'.Puyan Lotfi2018-01-103-3/+3
| | | | | | | | | | Planning to add support for named vregs. This puts is in a conundrum since physregs are named as well. To rectify this we need to use a sigil other than '%' for physregs in MIR. We've settled on using '$' for physregs but first we must repurpose it from external symbols using it, which is what this commit is all about. We think '&' will have familiar semantics for C/C++ users. llvm-svn: 322146
* [ORC] Re-apply r321838 again with a workaround for a bug present in the libcxxLang Hames2018-01-102-0/+318
| | | | | | | | | | | | | version being used on some of the green dragon builders (plus a clang-format). Workaround: AsynchronousSymbolQuery and VSO want to work with JITEvaluatedSymbols anyway, so just use them (instead of JITSymbol, which happens to tickle the bug). The libcxx bug being worked around was fixed in r276003, and there are plans to update the offending builders. llvm-svn: 322140
* LowerTypeTests: Add limited support for aliasesVlad Tsyrklevich2018-01-102-0/+83
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: LowerTypeTests moves some function definitions from individual object files to the merged module, leaving a stub to be called in the merged module's jump table. If an alias was pointing to such a function definition LowerTypeTests would fail because the alias would be left without a definition to point to. This change 1) emits information about aliases to the ThinLTO summary, 2) replaces aliases pointing to function definitions that are moved to the merged module with function declarations, and 3) re-emits those aliases in the merged module pointing to the correct function definitions. The patch does not correctly fix all possible mis-uses of aliases in LowerTypeTests. For example, it does not handle aliases with a different type from the pointed to function. The addition of alias data increases the size of Chrome build artifacts by less than 1%. Reviewers: pcc Reviewed By: pcc Subscribers: mehdi_amini, eraman, mgrang, llvm-commits, eugenis, kcc Differential Revision: https://reviews.llvm.org/D41741 llvm-svn: 322139
* [LoopRotate] Detect loops with indirect branches better (we're giving up on ↵Michael Zolotukhin2018-01-091-1/+1
| | | | | | them). llvm-svn: 322137
* Reland "Emit Function IDs table for Control Flow Guard"Adrian McCarthy2018-01-099-1/+153
| | | | | | | | | | | | | | | | | Adds option /guard:cf to clang-cl and -cfguard to cc1 to emit function IDs of functions that have their address taken into a section named .gfids$y for compatibility with Microsoft's Control Flow Guard feature. The original patch didn't have the lit.local.cfg file that restricts the new test to x86, thus the new test was failing on the non-x86 bots. Differential Revision: https://reviews.llvm.org/D40531 The reverts r322008, which was a revert of r322005. This reverts commit a05b89f9aca70597dc79fe97bc49b50b51f525ba. llvm-svn: 322136
* [WebAssembly] Add COMDAT supportSam Clegg2018-01-094-14/+141
| | | | | | | | | | | | | | This adds COMDAT support to the Wasm object-file format. Spec: https://github.com/WebAssembly/tool-conventions/pull/31 Corresponding LLD change: https://bugs.llvm.org/show_bug.cgi?id=35533, and D40845 Patch by Nicholas Wilson Differential Revision: https://reviews.llvm.org/D40844 llvm-svn: 322135
* [DWARFv5] MC support for MD5 file checksumsPaul Robinson2018-01-0910-34/+92
| | | | | | | Extend .file directive syntax to allow specifying an MD5 checksum for the source file. Emit the checksums in DWARF v5 line tables. llvm-svn: 322134
* Tidy some grammar in some commentsEric Christopher2018-01-092-4/+4
| | | | llvm-svn: 322133
* Use a MCExpr for the size of MCFillFragment.Rafael Espindola2018-01-093-16/+18
| | | | | | | This allows the size to be found during ralaxation. This fixes pr35858. llvm-svn: 322131
* [WebAssembly] MC: Use zero for provisional value of undefined symbolsSam Clegg2018-01-091-2/+2
| | | | | | | | | | This is more in line with what happens in the final executable when symbols are undefined (i.e. weak references). Differential Revision: https://reviews.llvm.org/D41840 llvm-svn: 322130
* [IPSCCP] Remove calls without side effectsChris Bieneman2018-01-092-1/+6
| | | | | | | | | | | | | | | Summary: When performing constant propagation for call instructions we have historically replaced all uses of the return from a call, but not removed the call itself. This is required for correctness if the calls have side effects, however the compiler should be able to safely remove calls that don't have side effects. This allows the compiler to completely fold away calls to functions that have no side effects if the inputs are constant and the output can be determined at compile time. Reviewers: davide, sanjoy, bruno, dberlin Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D38856 llvm-svn: 322125
* [PowerPC] Manually schedule the prologue and epilogueStefan Pintilie2018-01-091-6/+62
| | | | | | | | | | | | | | | | | | | | | This patch makes the following changes to the schedule of instructions in the prologue and epilogue. The stack pointer update is moved down in the prologue so that the callee saves do not have to wait for the update to happen. Saving the lr is moved down in the prologue to hide the latency of the mflr. The stack pointer is moved up in the epilogue so that restoring of the lr can happen sooner. The mtlr is moved up in the epilogue so that it is away form the blr at the end of the epilogue. The latency of the mtlr can now be hidden by the loads of the callee saved registers. This commit is almost identical to this one: r322036 except that two warnings that broke build bots have been fixed. The revision number is D41737 as before. llvm-svn: 322124
* Don't create MCFillFragment directly.Rafael Espindola2018-01-092-32/+15
| | | | | | Instead use higher level APIs that take care of most bookkeeping. llvm-svn: 322123
* [WebAssembly] Explicitly specify function/global index space in YAMLSam Clegg2018-01-092-2/+6
| | | | | | | | | | | These indexes are useful because they are not always zero based and functions and globals are referenced elsewhere by their index. This matches what we already do for the type index space. Differential Revision: https://reviews.llvm.org/D41877 llvm-svn: 322121
* [SelectionDAG] Fixed f16-from-vector promotion problemTim Renouf2018-01-091-1/+7
| | | | | | | | | | | | | | | | | | Summary: In the case of an fp_extend of v1f16 to v1f32 where the v1f16 is the result of a bitcast from i16, avoid creating an illegal fp16_to_fp where the input is not a vector and the result is a v1f32. V2: The fix is now to avoid vector scalarization creating a v1->scalar bitcast. Reviewers: srhines, t.p.northover Subscribers: nhaehnle, llvm-commits, dstuttard, t-tye, yaxunl, wdng, kzhuravl, arsenm Differential Revision: https://reviews.llvm.org/D41126 llvm-svn: 322120
* [AMDGPU] Fixed incorrect uniform branch conditionTim Renouf2018-01-091-0/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | Summary: I had a case where multiple nested uniform ifs resulted in code that did v_cmp comparisons, combining the results with s_and_b64, s_or_b64 and s_xor_b64 and using the resulting mask in s_cbranch_vccnz, without first ensuring that bits for inactive lanes were clear. There was already code for inserting an "s_and_b64 vcc, exec, vcc" to clear bits for inactive lanes in the case that the branch is instruction selected as s_cbranch_scc1 and is then changed to s_cbranch_vccnz in SIFixSGPRCopies. I have added the same code into SILowerControlFlow for the case that the branch is instruction selected as s_cbranch_vccnz. This de-optimizes the code in some cases where the s_and is not needed, because vcc is the result of a v_cmp, or multiple v_cmp instructions combined by s_and/s_or. We should add a pass to re-optimize those cases. Reviewers: arsenm, kzhuravl Subscribers: wdng, yaxunl, t-tye, llvm-commits, dstuttard, timcorringham, nhaehnle Differential Revision: https://reviews.llvm.org/D41292 llvm-svn: 322119
* NewGVN: Fix PR/33367, which was causing us to delete non-copy intrinsics ↵Daniel Berlin2018-01-091-2/+5
| | | | | | accidentally in some rare cases llvm-svn: 322115
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