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* [SystemZ] Tweak integer comparison codeRichard Sandiford2013-09-066-121/+122
| | | | | | | | | | | | | | | | | | | The architecture has many comparison instructions, including some that extend one of the operands. The signed comparison instructions use sign extensions and the unsigned comparison instructions use zero extensions. In cases where we had a free choice between signed or unsigned comparisons, we were trying to decide at lowering time which would best fit the available instructions, taking things like extension type into account. The code to do that was getting increasingly hairy and was also making some bad decisions. E.g. when comparing the result of two LLCs, it is better to use CR rather than CLR, since CR can be fused with a branch while CLR can't. This patch removes the lowering code and instead adds an operand to integer comparisons to say whether signed comparison is required, whether unsigned comparison is required, or whether either is OK. We can then leave the choice of instruction up to the normal isel code. llvm-svn: 190138
* [mips][msa] Sorted MSA_BIT_[BHWD]_DESC_BASE into ascending order of element sizeDaniel Sanders2013-09-061-16/+16
| | | | | | No functional change llvm-svn: 190134
* [mips][msa] Made the operand register sets optional for the 3R formatDaniel Sanders2013-09-061-460/+280
| | | | | | | | Their default is to be the same as the result register set. No functional change llvm-svn: 190133
* [mips][msa] Made the InstrItinClass argument optional since it is always ↵Daniel Sanders2013-09-061-600/+607
| | | | | | | | NoItinerary at the moment. No functional change llvm-svn: 190131
* [SystemZ] Use XC for a memset of 0Richard Sandiford2013-09-061-8/+21
| | | | llvm-svn: 190130
* Use type helper functions.Matt Arsenault2013-09-063-4/+3
| | | | llvm-svn: 190113
* Teach CodeGenPrepare about address spacesMatt Arsenault2013-09-061-4/+2
| | | | llvm-svn: 190112
* R600: Coding styleTom Stellard2013-09-051-6/+4
| | | | llvm-svn: 190110
* [X86] Perform VSELECT DAG combines also before DAG type legalization.Juergen Ributzka2013-09-051-10/+11
| | | | | | | | | | | | If the DAG already has only legal types, then the second round of DAG combines is skipped. In this case VSELECT+SETCC patterns that match a more efficient instruction (e.g. min/max) are never recognized. This fix allows VSELECT+SETCC combines if the types are already legal before DAG type legalization. Reviewer: Nadav llvm-svn: 190105
* Fixed a crash in the integrated assembler for Mach-O when a symbol differenceKevin Enderby2013-09-051-0/+4
| | | | | | | | | | | | | expression uses an assembler temporary symbol from an assignment.  In this case the symbol does not have a fragment so the use of getFragment() would be NULL and caused a crash. In the case of an assembler temporary symbol we want to use the AliasedSymbol (if any) which will create a local relocation entry, but if it is not an assembler temporary symbol then let it use that symbol with an external relocation entry. rdar://9356266 llvm-svn: 190096
* Consistently use dbgs() in debug printingMatt Arsenault2013-09-054-17/+17
| | | | llvm-svn: 190093
* R600: Fix i64 to i32 trunc on SIMatt Arsenault2013-09-051-0/+1
| | | | llvm-svn: 190091
* Remove unused argument.Rafael Espindola2013-09-051-3/+1
| | | | llvm-svn: 190090
* Improve handling of .file, .include and .incbin directives toYunzhong Gao2013-09-051-12/+16
| | | | | | | | | allow escaped octal character sequences. The patch was discussed in Phabricator. See: http://llvm-reviews.chandlerc.com/D1289 llvm-svn: 190089
* Debug Info: Use identifier to reference DIType in base type field ofManman Ren2013-09-055-4/+97
| | | | | | | | | | | | | | | | | | | | | | ptr_to_member. We introduce a new class DITypeRef that represents a reference to a DIType. It wraps around a Value*, which can be either an identifier in MDString or an actual MDNode. The class has a helper function "resolve" that finds the actual MDNode for a given DITypeRef. We specialize getFieldAs to return a field that is a reference to a DIType. To correctly access the base type field of ptr_to_member, getClassType now calls getFieldAs<DITypeRef> to return a DITypeRef. Also add a typedef for DITypeIdentifierMap and a helper generateDITypeIdentifierMap in DebugInfo.h. In DwarfDebug.cpp, we keep a DITypeIdentifierMap and call generateDITypeIdentifierMap to actually populate the map. Verifier is updated accordingly. llvm-svn: 190081
* R600: Add support for local memory atomic addTom Stellard2013-09-057-14/+78
| | | | llvm-svn: 190080
* R600: Expand SELECT nodes rather than custom lowering themTom Stellard2013-09-052-15/+6
| | | | llvm-svn: 190079
* R600: Fix incorrect LDS size calculationTom Stellard2013-09-052-4/+14
| | | | | | | GlobalAdderss nodes that appeared in more than one basic block were being counted twice. llvm-svn: 190078
* R600/SI: Don't emit S_WQM_B64 instruction for compute shadersTom Stellard2013-09-051-1/+2
| | | | llvm-svn: 190077
* R600: Fix segfault in R600TextureIntrinsicReplacerTom Stellard2013-09-051-0/+3
| | | | | | | | | | This pass was segfaulting when it ran into a non-intrinsic function call. Function calls are not supported, so now instead of segfaulting, we will get an assertion failure with a nice error message. I'm not sure how to test this using lit. llvm-svn: 190076
* Move accelerator table defines and constants to Dwarf.h sinceEric Christopher2013-09-055-56/+30
| | | | | | | | we're proposing it for DWARF5. No functional change intended. llvm-svn: 190074
* Reformat.Eric Christopher2013-09-052-99/+103
| | | | llvm-svn: 190064
* [ARMv8] Implement the new DMB/DSB operands.Joey Gouly2013-09-057-20/+27
| | | | | | | This removes the custom ISD Node: MEMBARRIER and replaces it with an intrinsic. llvm-svn: 190055
* Add AArch32 DCPS{1,2,3} and HLT instructions.Richard Barton2013-09-054-7/+47
| | | | | | | | | | | | | | | | | These were pretty straightforward instructions, with some assembly support required for HLT. The ARM assembler is keen to split the instruction mnemonic into a (non-existent) 'H' instruction with the LT condition code. An exception for HLT is needed. HLT follows the same rules as BKPT when in IT blocks, so the special BKPT hadling code has been adapted to handle HLT also. Regression tests added including diagnostic tests for out of range immediates and illegal condition codes, as well as negative tests for pre-ARMv8. llvm-svn: 190053
* Reverting 190043 for now.Tilmann Scheller2013-09-053-23/+3
| | | | | | | Solution is not sufficient to prevent 'mov pc, lr' being emitted for jump table code. Test case doesn't trigger the added functionality. llvm-svn: 190047
* ARM: Add GPR register class excluding LR for use with the ADR instruction.Tilmann Scheller2013-09-053-3/+23
| | | | | | | | | This improves code generation for jump tables by avoiding the emission of "mov pc, lr" which could fool the processor into believing this is a return from a function causing mispredicts. The code generation logic for jump tables uses ADR to materialize the address of the jump target. Patch by Daniel Stewart! llvm-svn: 190043
* [SystemZ] Add NC, OC and XCRichard Sandiford2013-09-057-46/+170
| | | | | | | For now these are just used to handle scalar ANDs, ORs and XORs in which all operands are memory. llvm-svn: 190041
* Declare missing dependency on AliasAnalysis. Patch by Liu Xin!Nick Lewycky2013-09-051-0/+1
| | | | llvm-svn: 190035
* [Sparc] Correctly handle call to functions with ReturnsTwice attribute.Venkatraman Govindaraju2013-09-054-4/+46
| | | | | | | | | | | | In sparc, setjmp stores only the registers %fp, %sp, %i7 and %o7. longjmp restores the stack, and the callee-saved registers (all local/in registers: %i0-%i7, %l0-%l7) using the stored %fp and register windows. However, this does not guarantee that the longjmp will restore the registers, as they were when the setjmp was called. This is because these registers may be clobbered after returning from setjmp, but before calling longjmp. This patch prevents the registers %i0-%i5, %l0-l7 to live across the setjmp call using the register mask. llvm-svn: 190033
* Fix comments to reflect reality.Bill Wendling2013-09-051-6/+2
| | | | llvm-svn: 190021
* Formatting.Eric Christopher2013-09-051-2/+2
| | | | llvm-svn: 190019
* mi-sched: Force bottom up scheduling for generic targets.Andrew Trick2013-09-041-3/+23
| | | | | | | | | Fast register pressure tracking currently only takes effect during bottom up scheduling. Forcing this is a bit faster and simpler for targets that don't have many scheduling constraints and don't need top-down scheduling. llvm-svn: 190014
* Add names for mach-o permissions bits and use the symbol names in place of ↵Nick Kledzik2013-09-041-2/+4
| | | | | | magic numbers llvm-svn: 190013
* Add missing header line.Bill Wendling2013-09-041-0/+1
| | | | llvm-svn: 190004
* Use ArrayRef instead of explicit container.Bill Wendling2013-09-041-2/+2
| | | | llvm-svn: 190003
* Remove hack ensuring that darwin didn't produce dwarf > 3 for modulesEric Christopher2013-09-041-5/+1
| | | | | | | | without a limiting factor. Update all testcases accordingly. llvm-svn: 190002
* Revert "Revert r189902 as the workaround shouldn't be necessary anymore."Eric Christopher2013-09-041-1/+5
| | | | | | Needs testcase updates. llvm-svn: 190000
* Revert r189902 as the workaround shouldn't be necessary anymore.Eric Christopher2013-09-041-5/+1
| | | | llvm-svn: 189999
* comment typoAndrew Trick2013-09-041-1/+1
| | | | llvm-svn: 189997
* Remove dead subtree limit code.Andrew Trick2013-09-041-9/+0
| | | | llvm-svn: 189995
* -view-misched-dags, better pruning.Andrew Trick2013-09-041-1/+1
| | | | llvm-svn: 189994
* mi-sched: DEBUG cleanup, call tracePick for unidirectional scheduling.Andrew Trick2013-09-041-0/+2
| | | | llvm-svn: 189993
* 80 columnsAndrew Trick2013-09-041-2/+2
| | | | llvm-svn: 189992
* mi-sched: Suppress register pressure tracking when the scheduling window is ↵Andrew Trick2013-09-041-16/+29
| | | | | | | | | | too small. If the instruction window is < NumRegs/2, pressure tracking is not likely to be effective. The scheduler has to process a very large number of tiny blocks. We want this to be fast. llvm-svn: 189991
* mi-sched: Load clustering is a bit to expensive to enable unconditionally.Andrew Trick2013-09-041-1/+1
| | | | llvm-svn: 189990
* mi-sched: Reuse an invalid HazardRecognizer to save compile time.Andrew Trick2013-09-041-6/+14
| | | | llvm-svn: 189989
* mi-sched: bypass heuristic checks when regpressure tracking is disabled.Andrew Trick2013-09-042-27/+32
| | | | llvm-svn: 189988
* Added -misched-regpressure option.Andrew Trick2013-09-042-21/+51
| | | | | | | | Register pressure tracking is half the complexity of the scheduler. It's useful to be able to turn it off for compile time and performance comparisons. llvm-svn: 189987
* Rename some variables to match the style guide.Rafael Espindola2013-09-041-6/+6
| | | | | | I am about to patch this code, and this makes the diff far more readable. llvm-svn: 189982
* R600: Use shared op optimization when checking cycle compatibilityVincent Lejeune2013-09-041-0/+2
| | | | llvm-svn: 189981
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