mi-sched: bypass heuristic checks when regpressure tracking is disabled.

llvm-svn: 189988

2 files changed, 32 insertions, 27 deletions

diff --git a/llvm/lib/CodeGen/MachineScheduler.cpp b/llvm/lib/CodeGen/MachineScheduler.cpp
index 7de7f390283..6b9dd3eb813 100644
--- a/llvm/lib/CodeGen/MachineScheduler.cpp
+++ b/llvm/lib/CodeGen/MachineScheduler.cpp
@@ -2363,30 +2363,32 @@ void ConvergingScheduler::tryCandidate(SchedCandidate &Cand,
                                        const RegPressureTracker &RPTracker,
                                        RegPressureTracker &TempTracker) {
 
-  // Always initialize TryCand's RPDelta.
-  if (Zone.isTop()) {
-    TempTracker.getMaxDownwardPressureDelta(
-      TryCand.SU->getInstr(),
-      TryCand.RPDelta,
-      DAG->getRegionCriticalPSets(),
-      DAG->getRegPressure().MaxSetPressure);
-  }
-  else {
-    if (VerifyScheduling) {
-      TempTracker.getMaxUpwardPressureDelta(
+  if (DAG->shouldTrackPressure()) {
+    // Always initialize TryCand's RPDelta.
+    if (Zone.isTop()) {
+      TempTracker.getMaxDownwardPressureDelta(
         TryCand.SU->getInstr(),
-        &DAG->getPressureDiff(TryCand.SU),
         TryCand.RPDelta,
         DAG->getRegionCriticalPSets(),
         DAG->getRegPressure().MaxSetPressure);
     }
     else {
-      RPTracker.getUpwardPressureDelta(
-        TryCand.SU->getInstr(),
-        DAG->getPressureDiff(TryCand.SU),
-        TryCand.RPDelta,
-        DAG->getRegionCriticalPSets(),
-        DAG->getRegPressure().MaxSetPressure);
+      if (VerifyScheduling) {
+        TempTracker.getMaxUpwardPressureDelta(
+          TryCand.SU->getInstr(),
+          &DAG->getPressureDiff(TryCand.SU),
+          TryCand.RPDelta,
+          DAG->getRegionCriticalPSets(),
+          DAG->getRegPressure().MaxSetPressure);
+      }
+      else {
+        RPTracker.getUpwardPressureDelta(
+          TryCand.SU->getInstr(),
+          DAG->getPressureDiff(TryCand.SU),
+          TryCand.RPDelta,
+          DAG->getRegionCriticalPSets(),
+          DAG->getRegPressure().MaxSetPressure);
+      }
     }
   }
 
@@ -2403,8 +2405,9 @@ void ConvergingScheduler::tryCandidate(SchedCandidate &Cand,
 
   // Avoid exceeding the target's limit. If signed PSetID is negative, it is
   // invalid; convert it to INT_MAX to give it lowest priority.
-  if (tryPressure(TryCand.RPDelta.Excess, Cand.RPDelta.Excess, TryCand, Cand,
-                  RegExcess))
+  if (DAG->shouldTrackPressure() && tryPressure(TryCand.RPDelta.Excess,
+                                                Cand.RPDelta.Excess,
+                                                TryCand, Cand, RegExcess))
     return;
 
   // For loops that are acyclic path limited, aggressively schedule for latency.
@@ -2412,8 +2415,9 @@ void ConvergingScheduler::tryCandidate(SchedCandidate &Cand,
     return;
 
   // Avoid increasing the max critical pressure in the scheduled region.
-  if (tryPressure(TryCand.RPDelta.CriticalMax, Cand.RPDelta.CriticalMax,
-                  TryCand, Cand, RegCritical))
+  if (DAG->shouldTrackPressure() && tryPressure(TryCand.RPDelta.CriticalMax,
+                                                Cand.RPDelta.CriticalMax,
+                                                TryCand, Cand, RegCritical))
     return;
 
   // Keep clustered nodes together to encourage downstream peephole
@@ -2435,8 +2439,9 @@ void ConvergingScheduler::tryCandidate(SchedCandidate &Cand,
     return;
   }
   // Avoid increasing the max pressure of the entire region.
-  if (tryPressure(TryCand.RPDelta.CurrentMax, Cand.RPDelta.CurrentMax,
-                  TryCand, Cand, RegMax))
+  if (DAG->shouldTrackPressure() && tryPressure(TryCand.RPDelta.CurrentMax,
+                                                Cand.RPDelta.CurrentMax,
+                                                TryCand, Cand, RegMax))
     return;
 
   // Avoid critical resource consumption and balance the schedule.
diff --git a/llvm/lib/CodeGen/ScheduleDAGInstrs.cpp b/llvm/lib/CodeGen/ScheduleDAGInstrs.cpp
index 33cdea6f19c..d940dbcf9f2 100644
--- a/llvm/lib/CodeGen/ScheduleDAGInstrs.cpp
+++ b/llvm/lib/CodeGen/ScheduleDAGInstrs.cpp
@@ -185,9 +185,6 @@ void ScheduleDAGInstrs::enterRegion(MachineBasicBlock *bb,
   RegionBegin = begin;
   RegionEnd = end;
   NumRegionInstrs = regioninstrs;
-  MISUnitMap.clear();
-
-  ScheduleDAG::clearDAG();
 }
 
 /// Close the current scheduling region. Don't clear any state in case the
@@ -703,6 +700,9 @@ void ScheduleDAGInstrs::buildSchedGraph(AliasAnalysis *AA,
                                                        : ST.useAA();
   AliasAnalysis *AAForDep = UseAA ? AA : 0;
 
+  MISUnitMap.clear();
+  ScheduleDAG::clearDAG();
+
   // Create an SUnit for each real instruction.
   initSUnits();