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* [DAG] fix formatting; NFCSanjay Patel2016-10-111-72/+68
| | | | llvm-svn: 283878
* [LCSSA] Implement linear algorithm for the isRecursivelyLCSSAFormIgor Laevsky2016-10-114-39/+49
| | | | | | | | For each block check that it doesn't have any uses outside of it's innermost loop. Differential Revision: https://reviews.llvm.org/D25364 llvm-svn: 283877
* [Thumb] Save/restore high registers in Thumb1 pro/epiloguesOliver Stannard2016-10-113-24/+368
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The high registers are not allocatable in Thumb1 functions, but they could still be used by inline assembly, so we need to save and restore the callee-saved high registers (r8-r11) in the prologue and epilogue. This is complicated by the fact that the Thumb1 push and pop instructions cannot access these registers. Therefore, we have to move them down into low registers before pushing, and move them back after popping into low registers. In most functions, we will have low registers that are also being pushed/popped, which we can use as the temporary registers for saving/restoring the high registers. However, this is not guaranteed, so we may need to push some extra low registers to ensure that the high registers can be saved/restored. For correctness, it would be sufficient to use just one low register, but if we have enough low registers available then we only need one push/pop instruction, rather than one per high register. We can also use the argument/return registers when they are not live, and the link register when saving (but not restoring), reducing the number of extra registers we need to push. There are still a few extreme edge cases where we need two push/pop instructions, because not enough low registers can be made live in the prologue or epilogue. In addition to the regression tests included here, I've also tested this using a script to generate functions which clobber different combinations of registers, have different numbers of argument and return registers (including variadic arguments), allocate different fixed sized objects on the stack, and do or don't use variable sized allocas and the __builtin_return_address intrinsic (all of which affect the available registers in the prologue and epilogue). I ran these functions in a test harness which verifies that all of the callee-saved registers are correctly preserved. Differential Revision: https://reviews.llvm.org/D24228 llvm-svn: 283867
* [ARM] Fix registers clobbered by SjLj EH on soft-float targetsOliver Stannard2016-10-114-2/+15
| | | | | | | | | | | | | | | | | | | Currently, the Int_eh_sjlj_dispatchsetup intrinsic is marked as clobbering all registers, including floating-point registers that may not be present on the target. This is technically true, as we could get linked against code that does use the FP registers, but that will not actually work, as the soft-float code cannot save and restore the FP registers. SjLj exception handling can only work correctly if either all or none of the code is built for a target with FP registers. Therefore, we can assume that, when Int_eh_sjlj_dispatchsetup is compiled for a soft-float target, it is only going to be linked against other soft-float code, and so only clobbers the general-purpose registers. This allows us to check that no non-savable registers are clobbered when generating the prologue/epilogue. Differential Revision: https://reviews.llvm.org/D25180 llvm-svn: 283866
* [AArch64] Allow label arithmetic with add/sub/cmpDiana Picus2016-10-113-26/+44
| | | | | | | | | | | | | Allow instructions such as 'cmp w0, #(end - start)' by folding the expression into a constant. For ELF, we fold only if the symbols are in the same section. For MachO, we fold if the expression contains only symbols that are not linker visible. Fixes https://llvm.org/bugs/show_bug.cgi?id=18920 Differential Revision: https://reviews.llvm.org/D23834 llvm-svn: 283862
* Fix formatting in findRegisterUseOperandIdx. NFC.Fraser Cormack2016-10-111-7/+5
| | | | llvm-svn: 283860
* Revert "Codegen: Tail-duplicate during placement."Daniel Jasper2016-10-113-330/+41
| | | | | | | | | This reverts commit r283842. test/CodeGen/X86/tail-dup-repeat.ll causes and llc crash with our internal testing. I'll share a link with you. llvm-svn: 283857
* Make RandomNumberGenerator compatible with <random>Mehdi Amini2016-10-111-1/+1
| | | | | | | | | | | | | LLVM's RandomNumberGenerator wasn't compatible with the random distribution from <random>. Fixes PR25105 Patch by: Serge Guelton <serge.guelton@telecom-bretagne.eu> Differential Revision: https://reviews.llvm.org/D25443 llvm-svn: 283854
* Tune isHotFunction/isColdFunctionDehao Chen2016-10-111-6/+2
| | | | | | | | | | | | Summary: This patch sets function as hot if function's entry count is hot/cold. Reviewers: eraman, davidxl Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D25048 llvm-svn: 283852
* Fix warning; NFCMatthias Braun2016-10-111-2/+2
| | | | llvm-svn: 283851
* MIRParser: generic register operands with typesMatthias Braun2016-10-112-2/+3
| | | | | | This should fix the fallout of r283848. llvm-svn: 283850
* MIRParser: Rewrite register info initialization; mostly NFCMatthias Braun2016-10-114-108/+179
| | | | | | | | | | | | | | | | | | | | | | This changes MachineRegisterInfo to be initializes after parsing all instructions. This is in preparation for upcoming commits that allow the register class specification on the operand or deduce them from the MCInstrDesc. This commit removes the unused feature of having nonsequential register numbers. This was confusing anyway as the vreg numbers would be different after parsing when you had "holes" in your numbering. This patch also introduces the concept of an incomplete virtual register. An incomplete virtual register may be used during .mir parsing to construct MachineOperands without knowing the exact register class (or register bank) yet. NFC except for some error messages. Differential Revision: https://reviews.llvm.org/D22397 llvm-svn: 283848
* Codegen: Tail-duplicate during placement.Kyle Butt2016-10-113-41/+330
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The tail duplication pass uses an assumed layout when making duplication decisions. This is fine, but passes up duplication opportunities that may arise when blocks are outlined. Because we want the updated CFG to affect subsequent placement decisions, this change must occur during placement. In order to achieve this goal, TailDuplicationPass is split into a utility class, TailDuplicator, and the pass itself. The pass delegates nearly everything to the TailDuplicator object, except for looping over the blocks in a function. This allows the same code to be used for tail duplication in both places. This change, in concert with outlining optional branches, allows triangle shaped code to perform much better, esepecially when the taken/untaken branches are correlated, as it creates a second spine when the tests are small enough. Issue from previous rollback fixed, and a new test was added for that case as well. Issue was worklist/scheduling/taildup issue in layout. Issue from 2nd rollback fixed, with 2 additional tests. Issue was tail merging/loop info/tail-duplication causing issue with loops that share a header block. Issue with early tail-duplication of blocks that branch to a fallthrough predecessor fixed with test case: tail-dup-branch-to-fallthrough.ll Differential revision: https://reviews.llvm.org/D18226 llvm-svn: 283842
* [libFuzzer] implement value profile for switch, increase the size of the PCs ↵Kostya Serebryany2016-10-113-4/+11
| | | | | | array, make sure we don't overflow it llvm-svn: 283841
* [libFuzzer] add switch testsKostya Serebryany2016-10-112-0/+38
| | | | llvm-svn: 283840
* [RegAllocGreedy] Attempt to split unspillable live intervalsDylan McKay2016-10-112-6/+11
| | | | | | | | | | | | | | | | | | | | | | | Summary: Previously, when allocating unspillable live ranges, we would never attempt to split. We would always bail out and try last ditch graph recoloring. This patch changes this by attempting to split all live intervals before performing recoloring. This fixes LLVM bug PR14879. I can't add test cases for any backends other than AVR because none of them have small enough register classes to trigger the bug. Reviewers: qcolombet Subscribers: MatzeB Differential Revision: https://reviews.llvm.org/D25070 llvm-svn: 283838
* [InstCombine] Transform !range metadata to !nonnull when combining loadsDavid Majnemer2016-10-111-2/+10
| | | | | | | | | | | | When combining an integer load with !range metadata that does not include 0 to a pointer load, make sure emit !nonnull metadata on the newly-created pointer load. This prevents the !nonnull metadata from being dropped during a ptrtoint/inttoptr pair. This fixes PR30597. Patch by Ariel Ben-Yehuda! Differential Revision: https://reviews.llvm.org/D25215 llvm-svn: 283836
* [AArch64][InstructionSelector] Teach how to select FP load/store.Quentin Colombet2016-10-111-0/+7
| | | | | | This patch allows to select 32 and 64-bit FP load and store. llvm-svn: 283832
* [AArch64][InstructionSelector] Teach the selector how to handle vector OR.Quentin Colombet2016-10-111-0/+2
| | | | | | | | | | This only adds the support for 64-bit vector OR. Adding more sizes is not difficult, but it requires a bigger refactoring because ORs work on any size, not necessarly the ones that match the width of the register width. Right now, this is not expressed in the legalization, so don't bother pushing the refactoring yet. llvm-svn: 283831
* [AArch64][MachineLegalizer] Mark v2s32 G_LOAD as legal.Quentin Colombet2016-10-111-1/+1
| | | | | | | Actually every 64-bit loads are legal, but right now the API does not offer a simple way to express that. llvm-svn: 283829
* Revert r283824 and r283823: Define DbiStreamBuilder::addDbgStream to add stream.Rui Ueyama2016-10-111-30/+2
| | | | | | This reverts commit r283824 and r283823 to fix buildbots. llvm-svn: 283828
* Fix a bug in DbiStreamBuilder::addDbgStream.Rui Ueyama2016-10-101-1/+1
| | | | | | This feature will be tested in LLD unit tests. llvm-svn: 283824
* Define DbiStreamBuilder::addDbgStream to add stream.Rui Ueyama2016-10-101-2/+30
| | | | | | | | | | Previously, there is no way to create a stream other than pre-defined special stream such as DBI or IPI. This patch adds a new method, addDbgStream, to add a debug stream to a PDB file. Differential Revision: https://reviews.llvm.org/D25356 llvm-svn: 283823
* Revert r283690, "MC: Remove unused entities."Peter Collingbourne2016-10-1016-15/+54
| | | | llvm-svn: 283814
* GlobalISel: select G_GLOBAL_VALUE uses on AArch64.Tim Northover2016-10-104-6/+32
| | | | llvm-svn: 283809
* GlobalISel: allow G_GLOBAL_VALUEs in AArch64 legalization.Tim Northover2016-10-101-0/+1
| | | | llvm-svn: 283808
* GlobalISel: support selecting G_GEP instructions.Tim Northover2016-10-101-1/+3
| | | | | | They're basically just an alias for G_ADD on AArch64. llvm-svn: 283807
* GlobalISel: support selecting constants on AArch64.Tim Northover2016-10-101-0/+10
| | | | llvm-svn: 283806
* Rename isHotFunction/isColdFunction to ↵Dehao Chen2016-10-102-14/+12
| | | | | | | | isFunctionEntryHot/isFunctionEntryCold. (NFC) This is in preparation for https://reviews.llvm.org/D25048 llvm-svn: 283805
* [SelectionDAGBuilder] Support llvm.flt.rounds on targets where i32 is not legalHal Finkel2016-10-102-0/+15
| | | | | | | | | | | Add integer expansion for FLT_ROUNDS_ for targets where i32 is not a legal type. Patch by Edward Jones, thanks! Differential Revision: https://reviews.llvm.org/D24459 llvm-svn: 283797
* Teach llvm::StripDebugInfo() about global variable !dbg attachments.Adrian Prantl2016-10-101-0/+9
| | | | | | | | | This is a regression introduced by the global variable ownership reversal performed in r281284. rdar://problem/28448075 llvm-svn: 283784
* Use unique_ptr in LLVMContextImpl's constant maps.Justin Lebar2016-10-103-28/+33
| | | | | | | | | | Reviewers: timshen Subscribers: cfe-commits Differential Revision: https://reviews.llvm.org/D25419 llvm-svn: 283767
* [ARM] Fix invalid VLDM/VSTM access when targeting Big Endian with NEONAlexandros Lamprineas2016-10-101-2/+12
| | | | | | | | | | | | | | | The instructions VLDM/VSTM can only access word-aligned memory locations and produce alignment fault if the condition is not met. The compiler currently generates VLDM/VSTM for v2f64 load/store regardless the alignment of the memory access. Instead, if a v2f64 load/store is not word-aligned, the compiler should generate VLD1/VST1. For each non double-word-aligned VLD1/VST1, a VREV instruction should be generated when targeting Big Endian. Differential Revision: https://reviews.llvm.org/D25281 llvm-svn: 283763
* Add return type for checkForValidSection parsing function. NFC Intended.Nirav Dave2016-10-101-41/+35
| | | | llvm-svn: 283761
* [X86] Prefer rotate by 1 over rotate by immZvi Rackover2016-10-101-4/+4
| | | | | | | | | | | | | Summary: Rotate by 1 is translated to 1 micro-op, while rotate with imm8 is translated to 2 micro-ops. Fixes pr30644. Reviewers: delena, igorb, craig.topper, spatel, RKSimon Differential Revision: https://reviews.llvm.org/D25399 llvm-svn: 283758
* This pass, fixing an erratum in some LEON 2 processors ensures that the SDIV ↵Chris Dewhurst2016-10-105-1/+18
| | | | | | | | instruction is not issued, but replaced by SDIVcc instead, which does not exhibit the error. Unit test included. Differential Review: https://reviews.llvm.org/D24660 llvm-svn: 283727
* Fix WebAssembly build after r283702.Daniel Jasper2016-10-101-2/+8
| | | | llvm-svn: 283723
* [AVX-512] Add missing pattern sext or zext from bytes to quad words with a ↵Craig Topper2016-10-101-0/+2
| | | | | | 128-bit load as input. llvm-svn: 283720
* [x86][inline-asm][llvm] accept 'v' constraintMichael Zuckerman2016-10-101-0/+15
| | | | | | | | | | | | | | Commit in the name of:Coby Tayree 1.'v' constraint for (x86) non-avx arch imitates the already implemented 'x' constraint, i.e. allows XMM{0-15} & YMM{0-15} depending on the apparent arch & mode (32/64). 2.for the avx512 arch it allows [X,Y,Z]MM{0-31} (mode dependent) This patch applies the needed changes to clang clang patch: https://reviews.llvm.org/D25004 Differential Revision: D25005 llvm-svn: 283717
* [AVR] Enable generation of the TableGen assembly writer tablesDylan McKay2016-10-101-2/+3
| | | | | | | This also changes the order of the statements in CMakeLists.txt to be alphabetical. llvm-svn: 283711
* [AVX-512] Port 128 and 256-bit memory->register sign/zero extend patterns ↵Craig Topper2016-10-091-0/+142
| | | | | | from SSE file. Also add a minimal set for 512-bit. llvm-svn: 283704
* [X86] Remove redundant patterns. The same pattern appears a few lines up.Craig Topper2016-10-091-6/+0
| | | | llvm-svn: 283703
* Move the global variables representing each Target behind accessor functionMehdi Amini2016-10-09100-331/+470
| | | | | | | | This avoids "static initialization order fiasco" Differential Revision: https://reviews.llvm.org/D25412 llvm-svn: 283702
* DAG: Setting Masked-Expand-Load as a variant of Masked-Load nodeElena Demikhovsky2016-10-096-37/+59
| | | | | | | | | | Masked-expand-load node represents load operation that loads a variable amount of elements from memory according to amount of "true" bits in the mask and expands the loaded elements according to their position in the mask vector. Right now, the node is used in intrinsics for VEXPAND* instructions. The work is done towards implementation of masked.expandload and masked.compressstore intrinsics. Differential Revision: https://reviews.llvm.org/D25322 llvm-svn: 283694
* [AVX-512] Fix execution domain for EVEX encoded VINSERTPS.Craig Topper2016-10-091-0/+2
| | | | llvm-svn: 283692
* MC: Remove unused entities.Peter Collingbourne2016-10-0916-54/+15
| | | | llvm-svn: 283691
* Target: Remove unused entities.Peter Collingbourne2016-10-0911-81/+4
| | | | llvm-svn: 283690
* [AVX-512] Add subvector insert and extract to load/store folding tables.Craig Topper2016-10-091-0/+25
| | | | llvm-svn: 283689
* [AVX-512] Add the vector down convert instructions to the store folding tables.Craig Topper2016-10-091-0/+24
| | | | llvm-svn: 283687
* [libFuzzer] make a test less flakyKostya Serebryany2016-10-091-1/+0
| | | | llvm-svn: 283686
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