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| author | Zvi Rackover <zvi.rackover@intel.com> | 2016-10-10 14:43:55 +0000 |
|---|---|---|
| committer | Zvi Rackover <zvi.rackover@intel.com> | 2016-10-10 14:43:55 +0000 |
| commit | 2a21f125bd077940713008a421c0112d5188038b (patch) | |
| tree | af8a4b119a146032a4f698799a983cfc3cd0c52a /llvm/lib | |
| parent | 8c7365a9fa20d636f5c49c8f2844f9508a929ba6 (diff) | |
| download | bcm5719-llvm-2a21f125bd077940713008a421c0112d5188038b.tar.gz bcm5719-llvm-2a21f125bd077940713008a421c0112d5188038b.zip | |
[X86] Prefer rotate by 1 over rotate by imm
Summary:
Rotate by 1 is translated to 1 micro-op, while rotate with imm8 is translated to 2 micro-ops.
Fixes pr30644.
Reviewers: delena, igorb, craig.topper, spatel, RKSimon
Differential Revision: https://reviews.llvm.org/D25399
llvm-svn: 283758
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/Target/X86/X86InstrShiftRotate.td | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/llvm/lib/Target/X86/X86InstrShiftRotate.td b/llvm/lib/Target/X86/X86InstrShiftRotate.td index 3b660683672..6303b6eaa30 100644 --- a/llvm/lib/Target/X86/X86InstrShiftRotate.td +++ b/llvm/lib/Target/X86/X86InstrShiftRotate.td @@ -609,19 +609,19 @@ def ROR64ri : RIi8<0xC1, MRM1r, (outs GR64:$dst), // Rotate by 1 def ROR8r1 : I<0xD0, MRM1r, (outs GR8 :$dst), (ins GR8 :$src1), "ror{b}\t$dst", - [(set GR8:$dst, (rotr GR8:$src1, (i8 1)))], + [(set GR8:$dst, (rotl GR8:$src1, (i8 7)))], IIC_SR>; def ROR16r1 : I<0xD1, MRM1r, (outs GR16:$dst), (ins GR16:$src1), "ror{w}\t$dst", - [(set GR16:$dst, (rotr GR16:$src1, (i8 1)))], + [(set GR16:$dst, (rotl GR16:$src1, (i8 15)))], IIC_SR>, OpSize16; def ROR32r1 : I<0xD1, MRM1r, (outs GR32:$dst), (ins GR32:$src1), "ror{l}\t$dst", - [(set GR32:$dst, (rotr GR32:$src1, (i8 1)))], + [(set GR32:$dst, (rotl GR32:$src1, (i8 31)))], IIC_SR>, OpSize32; def ROR64r1 : RI<0xD1, MRM1r, (outs GR64:$dst), (ins GR64:$src1), "ror{q}\t$dst", - [(set GR64:$dst, (rotr GR64:$src1, (i8 1)))], + [(set GR64:$dst, (rotl GR64:$src1, (i8 63)))], IIC_SR>; } // Constraints = "$src = $dst", SchedRW |
